Abstract: An apparatus for controlling an activation period of a word line of a volatile memory device is disclosed. The apparatus adjusts the activation period of the word line using a member for adjusting a pulse width of a pulse signal that activates the word line according to an operation mode of the volatile memory device.

Abstract: A portable system comprises a portable apparatus which performs a plurality of functions according to predetermined control information; and a supporting apparatus for the portable apparatus, the supporting apparatus comprising: a connecting part which is connectable to the portable apparatus; a storing part which stores the predetermined control information corresponding to the plurality of functions of the portable apparatus; and a controller which stores control information corresponding to a selected function among the plurality of functions in the storing part, and transmits the control information stored in the storing part to the portable apparatus for performing the selected function if the portable apparatus is connected to the connecting part.

Abstract: A broadcasting signal processing apparatus and a control method thereof are provided. The broadcasting signal processing apparatus includes a wireless antenna; a radio frequency (RF) module which tunes a broadcasting signal; a variable part which adjusts an impedance to match an impedance of the wireless antenna with an impedance of the RF module; and a controlling part which pre-stores impedance variable values for impedance matching and which controls the variable part to adjust the impedance based on one of the pre-stored impedance variable values corresponding to a broadcasting frequency of a selected broadcasting channel. The method includes tuning to a broadcasting frequency; determining whether an impedance used to match a wireless antenna with a radio frequency (RF) module is different from an impedance variable value; and if the impedance is different, adjusting the impedance.

Abstract: A class library footprint file for authenticating a dynamically loaded class library during the execution of a JAVA application and a JAVA application authentication method using the class library footprint file are provided. The class library footprint file includes: authentication information for verifying the integrity of one or more class libraries used by the JAVA application before the JAVA application is executed. A list of class libraries to be authenticated is provided, in advance, to a JAVA application.

Abstract: Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.

Abstract: The present invention relates to a method for preparing germinated brown rice that has better texture, is easier to cook and has higher safety from microbial contamination compared with conventional germinated brown rice, by controlling the conditions for the germination process, and to a germinated brown rice obtained therefrom. More particularly, improved germinated brown rice can be obtained by at least partially removing the skin, germinating the altered rice in slighted acid germination water and treating the germinated brown rice at elevated temperatures and pressures.

Abstract: A surface light source device includes a lamp body, a space dividing member, a discharge gas supplying member and a voltage applying part. The lamp body includes a flat shaped space and a fluorescent layer disposed in the flat shaped space to convert an invisible light into a visible light. The space dividing member divides the flat shaped space into a plurality of discharge spaces. The discharge gas supplying member is disposed to pass through the space dividing member and is fixed to the space dividing member, and supplies the discharge spaces with a discharge gas that generates the invisible light. The voltage applying part applies a discharge voltage to the discharge gas. Therefore, the lifetime of the surface light source device generating a planar light is increased, and the luminance of the light becomes uniform so that the display quality of an image is improved.

Abstract: Disclosed herein are a directional coupler which is implemented with strip lines for signal coupling and inter-digital capacitors for phase compensation, and a dual-band transmitter using the same. The directional coupler includes a first transmission device, a first directional coupling device for coupling a part of a signal from the first transmission device, a first inter-digital capacitor connected between the first transmission device and the first directional coupling device, a second transmission device, a second directional coupling device for coupling a part of a signal from the second transmission device, and a second inter-digital capacitor connected between the second transmission device and the second directional coupling device.

Abstract: A bit line sense amplifier control circuit includes a driving signal generating unit adapted and configured to generate first through third driving signals in response to a bit line sense amplifier enable signal and an overdrive enable signal for setting an overdrive period, and to disable a first driving signal which is enabled for an overdrive period in response to a refresh signal which is enabled at a refresh mode, and a bit line sense amplifier control signal generating unit adapted and configured to generate first and second bit line sense amplifier control signals in response to the first through third driving signals. As a result, an overdrive pulse is not generated at a refresh mode to remove an overdriving period, thereby reducing current consumption at a refresh mode.

Abstract: A power supply system of a display apparatus and a control method thereof comprising a DC (Direct current) converter to convert an AC (Alternating Current) voltage into a DC voltage; a PWM (Pulse Width Modulator) to generate a PWM signal; a transformer to receive the DC voltage of the DC converter and to output an AC voltage according to the PWM signal from the PWM; an output circuit to lower the AC voltage from the transformer and to supply the lowered voltage to various components; a sync signal supplier to generate a sync signal having a frequency equal to a frequency of a horizontal sync signal, which is externally input, to generate the PWM signal synchronized to the horizontal sync signal and to supply the sync signal to the PWM; and a controller to determine a power saving mode depending on whether the horizontal sync signal or a vertical sync signal is externally input, and to control the sync signal supplier to generate the sync signal having a frequency equal to the frequency of the horizontal sync

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract: Provided are a flexible bit rate code vector generation method and a wideband vocoder employing the same. This invention implements a flexible bit rate by getting three code vectors which are composed of 24, 16, and 8 pulses, at a time in a search process, through improvement of an algebraic codebook search process in a wideband AMR-WB vocoder. The method includes the steps of: performing a preprocess, wherein the preprocess divides a sub-frame by tracks and decides a pulse position having a maximum value in each track; among a plurality of pulses to be searched, fixing a same number of pulses as the tracks to the position with the maximum value of each track sequentially, and searching optimal positions having a minimum error with a target signal by combining two pulses in two consecutive tracks for the remaining pulses; and creating a code vector with flexible bit rate.

Abstract: A display device includes a displaying part which displays a picture based on a video signal output from a computer main body, a power supply which supplies driving power corresponding to one of a normal mode and a power saving mode, a power saving mode selection part which allows selection of the power saving mode, and a micro controller which controls the power supply to supply the driving power to the display device according to the power saving mode selected through the power saving mode selection part. Therefore, the display device can perform a power saving function by itself according to a selection by a user.

Abstract: A clock and data recovery apparatus reduces current consumption and enables easy integration. The inventive apparatus includes a first loop including a frequency/phase detection unit, a first charge pump unit, a multiplexing unit, a filtering unit, and a voltage controlled oscillator unit operating at a speed ¼ as fast as that of received data; a second loop having a phase detection unit operating at a speed ¼ as fast as a speed of received data, a second charge pump unit suitable for the phase detection unit, the multiplexing unit, the filtering unit, and the voltage controlled oscillator unit; a frequency lock detection unit for judging whether a frequency of a feedback clock signal falls within a desired frequency range; and a data recovery unit for recovering data from received data.

Abstract: Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A power supply system of a display apparatus and a control method thereof comprising a DC (Direct current) converter to convert an AC (Alternating Current) voltage into a DC voltage; a PWM (Pulse Width Modulator) to generate a PWM signal; a transformer to receive the DC voltage of the DC converter and to output an AC voltage according to the PWM signal from the PWM; an output circuit to lower the AC voltage from the transformer and to supply the lowered voltage to various components; a sync signal supplier to generate a sync signal having a frequency equal to a frequency of a horizontal sync signal, which is externally input, to generate the PWM signal synchronized to the horizontal sync signal and to supply the sync signal to the PWM; and a controller to determine a power saving mode depending on whether the horizontal sync signal or a vertical sync signal is externally input, and to control the sync signal supplier to generate the sync signal having a frequency equal to the frequency of the horizontal sync

Abstract: A method of detecting a crack in a disc loaded on a disc drive and a method of automatically lowering a target speed in response to the detection of a crack in order to stabilize the disc drive. According to the methods, it is automatically determined whether a disc loaded on a disc drive has a crack in a specific mode, and a target speed is automatically changed into a low speed when it is determined that the disc has a crack. Therefore, the crack state of the disc is exactly checked during action of the disc drive, the percentage of error occurrence is decreased, and the probability of damage to the disc is reduced.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: The present invention relates to a method for preparing germinated brown rice that has better texture, is easier to cook and has higher safety from microbial contamination compared with conventional germinated brown rice, by controlling the conditions for the germination process, and to a germinated brown rice obtained therefrom. More particularly, improved germinated brown rice can be obtained by at least partially removing the skin, germinating the altered rice in slighted acid germination water and treating the germinated brown rice at elevated temperatures and pressures.