Abstract: The present invention reduces complexity of computation as about 40% comparing to the conventional depth first tree search method. A method for searching an algebraic codebook in algebraic code excited linear prediction (ACELP) vocoding using a depth first tree method, includes the steps of: a) searching branches of predetermined levels to predict a branch in which optimum pulse is located; b) choosing a predetermined number of branches according to the search result of the step a) and removing residual branches; and c) searching the chosen branches and choosing optimum algebraic code.

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: A display device includes a displaying part which displays a picture based on a video signal output from a computer main body, a power supply which supplies driving power corresponding to one of a normal mode and a power saving mode, a power saving mode selection part which allows selection of the power saving mode, and a micro controller which controls the power supply to supply the driving power to the display device according to the power saving mode selected through the power saving mode selection part. Therefore, the display device can perform a power saving function by itself according to a selection by a user.

Abstract: A method of detecting a crack in a disc loaded on a disc drive and a method of automatically lowering a target speed in response to the detection of a crack in order to stabilize the disc drive. According to the methods, it is automatically determined whether a disc loaded on a disc drive has a crack in a specific mode, and a target speed is automatically changed into a low speed when it is determined that the disc has a crack. Therefore, the crack state of the disc is exactly checked during action of the disc drive, the percentage of error occurrence is decreased, and the probability of damage to the disc is reduced.

Abstract: A circuit for compensating a horizontal centering in a video display apparatus includes a control circuit, a horizontal centering compensation circuit, and a horizontal deflection output circuit. The circuit functions such that even when the video display mode of a multi-mode monitor is shifted, any biasing of the picture can be automatically minimized or prevented. The control unit counts the frequency of externally input video synchronizing signals to output a first switching control signal or a second switching control signal based on the counted result of the frequency of the video synchronizing signals. The horizontal centering compensation circuit provides a first power and a second power, the first and second powers having voltage levels and directions different from each other, to output the first power or the second power in response to the first switching control signal or the second switching control signal of the control unit.

Abstract: The present invention relates to a process for manufacturing polyethylene with a functional end group in the presence of metallocene catalyst and more particularly, to the process for manufacturing polyethylene with a functional end group in such a manner that a highly reactive functional group of alkyl-aluminum is easily introduced to the end of polymer via a selective chain transfer reaction in the presence of (1) metallocene catalyst represented by the following formula 1 and (2) a cocatalyst containing alkyl-aluminum compound as active ingredient.

Abstract: A duty cycle alteration circuit can simply alter a duty cycle of a pulse by using a Schmitt circuit in a monitor. The duty cycle alteration circuit includes: a microcomputer for outputting a waveform amplifying ratio control signal; an amplifying circuit for inputting and amplifying the waveform amplifying ratio control signal outputted by the microcomputer or a triangular wave and for outputting an amplified triangular wave; and a Schmitt circuit for establishing a logic “high” level and a logic “low” level centering around a reference level according to the amplified triangular wave supplied from the amplifying circuit and for changing a duty cycle on the basis of the logic “high” and “low” levels and for outputting a rectangular wave having an altered duty cycle.

Abstract: A video control circuit controls the gains for red(R), green(G), and blue(B) color video signals inputted to a monitor, the brightness and contrast of a video display on the monitor, and the bias of a cathode ray tube within the monitor. A microcomputer outputs, in an I2C manner, data for a control signal for controlling contrast, brightness, gain and/or bias. The data are inputted to an I2C data process/PWM signal generation section which converts the data to PWM signal outputs. Rectification sections rectify the PWM signal outputs to provide contrast, brightness, gain and cutoff voltage signals. Only two output terminals of the microcomputer are employed for outputting a clock signal and the data for the control signal so as to control contrast, brightness, gain and bias control signals according to output signals of the variable resistors VR11 and VR12 and a bias/grain control section. A clock signal is generated by the microcomputer in synchronization with the data DATA.

Abstract: A method for encoding a channel using a parallel convolutional encoder is disclosed. The method includes the steps of a first step for performing an encoding operation using a parallel convolutional encoder at the time when a data is inputted into a frame input data register for implementing a channel encoding operation and generating a code symbol, and a second step for storing the thusly generated code symbol into an interleaver RAM which is alternately selected by the frame unit.

Abstract: A display device having a set protecting function upon generation of an abnormal voltage includes a horizontal deflection circuit for providing a horizontal signal to a deflection yoke connector, a high voltage output circuit for supplying a high voltage to an anode in accordance with an oscillating signal applied from the horizontal deflection circuit, a power supply circuit for supplying power to the horizontal deflection circuit, and an abnormal voltage detector disposed between the deflection yoke connector, and the high voltage output circuit and the power supply circuit, for detecting whether the deflection yoke connector is connected and whether a part of the high voltage output circuit is damaged, to thereby control a power output of the power supply circuit in accordance with a detected result.

Abstract: An improved pitch searching time reducing method for a CELP vocoder using a Line Spectral Pair (LSP) frequency which is capable of significantly reducing the pitch search time by separating the speech signal using a first formant frequency of the line spectral pair of the digital type personal communication system, which includes the steps of computing a decimation interval of a pitch search interval using an LSP frequency of a first formant computed by a formant filter so as to compute a preparatory pitch of a given speech; determining a preparatory pitch to be used when searching a pitch by detecting a peak and a valley within each decimation interval; and computing a preparatory pitch by adapting a first formant frequency of an LSP computed by a formant filter with a decimation rate and performing a pitch search with respect to the obtained preparatory pitch.

Abstract: The present invention relates to the method to receive a speech signal, to perform a recognition weighting process on it, to synthesize a synthetic speech signal, to calculate an autocorrelation of the synthetic speech signal whose delay is a predetermined value and an autocorrelation whose delay is 0, to divide the square of the former by the latter, to calculate a pitch lag and a pitch filter coefficient by calculating only the part of a positive peak with skipping over the part of a negative peak by using the results from the dividing operation, and to calculate and output the pitch lag and the pitch filter coefficient by repeating the above process Thus, real-time implementation of CELP vocoder can be achieved.

Abstract: A method for processing an input speech signal to be applied to a CELP vocoder has the steps of obtaining preliminary pitch search intervals by a preprocessing autocorrelation expression from a pitch lag of a synthesized speech signal which is synthesized from a residual signal of the input speech signal; computing coefficients of pitch filter with respect to the preliminary pitches; searching a high interval in the autocorrelation; and removing the remaining interval other than the high interval in the pitch lag. Since the present invention proposes a speech processing method which uses only a high interval in autocorrelation of a voice waveform in pitch-searching, and where such a speech processing method is embodied in a CELP vocoder, total computation time of the CELP vocoder can be decreased 37% or more without lowering speech quality. Therefore, a digital signal processor, which is low in price and is slow in speed, can be embodied in a CELP vocoder.