Patents by Inventor Jin Chae

Jin Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12223031
    Abstract: This invention relates to a face recognition system and method capable of updating a registered face template.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: February 11, 2025
    Assignee: CMITECH CO., LTD.
    Inventor: Jang-Jin Chae
  • Publication number: 20240429080
    Abstract: Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.
    Type: Application
    Filed: September 5, 2024
    Publication date: December 26, 2024
    Inventors: Sunna Chung, Ryan Park, Jin Chae, Matthew Stanton Whitlock, Jonathan Kevin Lie, Athens Okoren
  • Patent number: 12106988
    Abstract: Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: October 1, 2024
    Assignee: Daewon Semiconductor Packaging Industrial Company
    Inventors: Sunna Chung, Ryan Park, Jin Chae, Matthew Stanton Whitlock, Jonathan Kevin Lie, Athens Okoren
  • Patent number: 12094978
    Abstract: An oxide semiconductor thin film transistor and a method of forming the oxide semiconductor thin film transistor are provided. The oxide semiconductor thin film transistor can include a semiconductor layer including a channel region, a source region and a drain region; a first gate insulating layer on the semiconductor layer; a gate electrode on the first gate insulating layer; a second gate insulating layer on the gate electrode; an auxiliary electrode on the second gate insulating layer; an interlayer insulating layer on the auxiliary electrode; and a source electrode and a drain electrode on the interlayer insulating layer, wherein the source region and the drain region being disposed at both sides of the channel region, wherein the gate electrode overlapping with the channel region, and the auxiliary electrode overlapping with the gate electrode.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: September 17, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hyuk Ji, Jin Chae Jeon, Jae Hyun Kim, Sun Young Choi, Mi Jin Jeong
  • Publication number: 20240247272
    Abstract: The present invention provides antisense oligonucleotides for the treatment of various T-type calcium channel ?1G subunit-related disorders, and more specifically, antisense oligonucleotides for inhibiting expression of the gene encoding Cav3.1, targeting SEQ ID NO: 1, for the treatment of various neuropsychiatric disorders, including Parkinson's disease, epilepsy, essential tremor, depression, anxiety disorders, and unconsciousness.
    Type: Application
    Filed: February 19, 2024
    Publication date: July 25, 2024
    Inventors: Dae Soo KIM, Jin Kuk KIM, Ye Won LEE, Eun Ji JUNG, Min Sung PARK, Sin Jeong LEE, Su Jin CHAE
  • Publication number: 20240153831
    Abstract: An apparatus and method for measuring air currents on the surface of a substrate, which can accurately measure the magnitude and direction of air currents on the surface of a wafer with wafer-type air current measurement sensors, are provided. The apparatus includes: a first air current measurement module measuring a magnitude of air currents on a surface of a first substrate, which is processed in accordance with a semiconductor manufacturing process; a second air current measurement module measuring a movement direction of the air currents; and a power module supplying power to the first and second air current measurement modules, wherein the first air current measurement module, the second air current measurement module, and the power module are mounted on a second substrate, which has the same shape as the first substrate.
    Type: Application
    Filed: October 19, 2023
    Publication date: May 9, 2024
    Inventors: Yong Jun SEO, Su Jin CHAE, Sang Hyun SON, Sang Min HA, Young Sik BANG, Jeong Mo HWANG, Dong Ok AHN
  • Patent number: 11974469
    Abstract: Disclosed is a display device and a method of manufacturing the same having improved reliability. In the display device, at least one of a plurality of dielectric films disposed between an oxide semiconductor layer and a light-emitting device includes a lower region disposed on the oxide semiconductor layer and an upper region disposed on the lower region, the upper region including a trap element configured to trap hydrogen, whereby reliability of a thin film transistor including the oxide semiconductor layer is improved.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: April 30, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: Jae Hyun Kim, Jin Chae Jeon, Sun Young Choi, Mi Jin Jeong, Jeoung In Lee
  • Publication number: 20230204354
    Abstract: The inventive concept provides a portable level measuring apparatus. The portable level measuring apparatus includes a sensor module having a sensor unit configured to measure an inclination of a measuring object and a wireless communication unit configured to transmit a measured information which is measured at the sensor unit; and a portable terminal connected to the sensor module through a wireless communication, and which displays the measured information, and wherein the sensor module combines with the portable terminal through a connector and which pairs immediately if separated with the portable terminal.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 29, 2023
    Applicant: SEMES CO., LTD.
    Inventors: Su Jin CHAE, Sang Min HA, Dong Ok AHN, Ho Hyeong LEE, Yong-Jun SEO, Sang Hyun SON, Hyeong Jun CHO
  • Publication number: 20230100373
    Abstract: The inventive concept provides a sensor station. The sensor station includes a body providing an inner space for storing a substrate-type sensor; a power source unit installed at the body and configured to transmit a power to the substrate-type sensor; a processing unit installed at the body and configured to process a data measured by the substrate-type sensor; and a communication unit installed at the body and configured to exchange a data with the substrate-type sensor and a server of a substrate treating system.
    Type: Application
    Filed: September 30, 2022
    Publication date: March 30, 2023
    Applicant: SEMES CO., LTD.
    Inventors: Sang Hyun SON, Yong-Jun SEO, Su Jin CHAE, Dong Ok AHN, Jae Hong KIM
  • Publication number: 20230083574
    Abstract: A temperature measuring apparatus with improved accuracy is provided. The temperature measuring apparatus comprises a test substrate having a thermal conductivity, a circuit board layer laminated on the test substrate and including a plurality of through holes exposing a top surface of the test substrate, bonding agent disposed in the plurality of through holes and having a thermal conductivity, and a plurality of sensors disposed on the bonding agent and for measuring a temperature.
    Type: Application
    Filed: May 5, 2022
    Publication date: March 16, 2023
    Inventors: Yong Jun SEO, Sang Hyun SON, Su Jin CHAE, Dong Ok AHN
  • Publication number: 20230005771
    Abstract: Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.
    Type: Application
    Filed: February 18, 2022
    Publication date: January 5, 2023
    Inventors: Sunna Chung, Ryan Park, Jin Chae, Matthew Stanton Whitlock, Jonathan Kevin Lie, Athens Okoren
  • Publication number: 20220318369
    Abstract: This invention relates to a face recognition system and method capable of updating a registered face template.
    Type: Application
    Filed: November 9, 2020
    Publication date: October 6, 2022
    Inventor: Jang-Jin CHAE
  • Publication number: 20220165821
    Abstract: Disclosed is a display device and a method of manufacturing the same having improved reliability. In the display device, at least one of a plurality of dielectric films disposed between an oxide semiconductor layer and a light-emitting device includes a lower region disposed on the oxide semiconductor layer and an upper region disposed on the lower region, the upper region including a trap element configured to trap hydrogen, whereby reliability of a thin film transistor including the oxide semiconductor layer is improved.
    Type: Application
    Filed: August 25, 2021
    Publication date: May 26, 2022
    Inventors: Jae Hyun Kim, Jin Chae Jeon, Sun Young Choi, Mi Jin Jeong, Jeoung In Lee
  • Patent number: 11271039
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Chi-Ho Kim, Min-Seon Kang, Hyun-Seok Kang, Hyo-June Kim, Jae-Geun Oh, Su-Jin Chae
  • Patent number: 11257700
    Abstract: Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 22, 2022
    Assignee: Daewon Semiconductor Packaging Industrial Company
    Inventors: Sunna Chung, Ryan Park, Jin Chae, Matthew Whitlock, Jonathan Lie, Athens Okoren
  • Patent number: 11189630
    Abstract: A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Gun Kang, Hyun Seok Kang, Deok Lae Ahn, Jae Geun Oh, Won Ki Joo, Su-Jin Chae
  • Publication number: 20210313470
    Abstract: An oxide semiconductor thin film transistor and a method of forming the oxide semiconductor thin film transistor are provided. The oxide semiconductor thin film transistor can include a semiconductor layer including a channel region, a source region and a drain region; a first gate insulating layer on the semiconductor layer; a gate electrode on the first gate insulating layer; a second gate insulating layer on the gate electrode; an auxiliary electrode on the second gate insulating layer; an interlayer insulating layer on the auxiliary electrode; and a source electrode and a drain electrode on the interlayer insulating layer, wherein the source region and the drain region being disposed at both sides of the channel region, wherein the gate electrode overlapping with the channel region, and the auxiliary electrode overlapping with the gate electrode.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 7, 2021
    Applicant: LG Display Co., Ltd.
    Inventors: Hyuk JI, Jin Chae JEON, Jae Hyun KIM, Sun Young CHOI, Mi Jin JEONG
  • Patent number: 11135223
    Abstract: The present invention provides compositions and methods for inhibiting Dkk-1 for treating or preventing an inflammatory or inflammatory-related disease or disorder.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 5, 2021
    Assignee: Yale University
    Inventors: Wook-Jin Chae, Alfred Bothwell
  • Publication number: 20200373353
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.
    Type: Application
    Filed: December 11, 2019
    Publication date: November 26, 2020
    Inventors: Chi-Ho KIM, Min-Seon KANG, Hyun-Seok KANG, Hyo-June KIM, Jae-Geun OH, Su-Jin CHAE
  • Patent number: D1015739
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: February 27, 2024
    Inventor: Rak Jin Chae