Patents by Inventor Jin Chae

Jin Chae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220242948
    Abstract: The present invention relates to an anti-L1CAM antibody specifically binding to L1CAM antigen or an antigen-binding fragment thereof, a chimeric antigen receptor comprising same, and uses thereof. The anti-L1CAM antibody or the antigen-binding fragment of the present invention is excellent in specificity and affinity to L1CAM and thus may be used in the treatment and diagnosis of cancers related to high expression of L1CAM and diseases related to inflammatory disorders. In particular, when the chimeric antigen receptor comprising the anti-L1CAM antibody of the present invention is expressed in effector cells such as T lymphocytes, the chimeric antigen receptor may be effectively used as immunotherapy for cancers related to L1CAM and inflammatory disorders.
    Type: Application
    Filed: October 21, 2019
    Publication date: August 4, 2022
    Inventors: Jin-A CHAE, Jae-Gyun JEONG, Dae Young KIM, Yu Jung KIM, Bin YOO
  • Publication number: 20220165821
    Abstract: Disclosed is a display device and a method of manufacturing the same having improved reliability. In the display device, at least one of a plurality of dielectric films disposed between an oxide semiconductor layer and a light-emitting device includes a lower region disposed on the oxide semiconductor layer and an upper region disposed on the lower region, the upper region including a trap element configured to trap hydrogen, whereby reliability of a thin film transistor including the oxide semiconductor layer is improved.
    Type: Application
    Filed: August 25, 2021
    Publication date: May 26, 2022
    Inventors: Jae Hyun Kim, Jin Chae Jeon, Sun Young Choi, Mi Jin Jeong, Jeoung In Lee
  • Patent number: 11279769
    Abstract: The invention provides improved compositions for adoptive cell therapies for cancers that express the glycoepitope STn on TAG-72.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 22, 2022
    Assignee: Helixmith Co., Ltd
    Inventors: Richard Morgan, Kevin Friedman, Seung Shin Yu, Jae-Gyun Jeong, Jin-A Chae
  • Patent number: 11271039
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Chi-Ho Kim, Min-Seon Kang, Hyun-Seok Kang, Hyo-June Kim, Jae-Geun Oh, Su-Jin Chae
  • Patent number: 11257700
    Abstract: Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 22, 2022
    Assignee: Daewon Semiconductor Packaging Industrial Company
    Inventors: Sunna Chung, Ryan Park, Jin Chae, Matthew Whitlock, Jonathan Lie, Athens Okoren
  • Patent number: 11189630
    Abstract: A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Gun Kang, Hyun Seok Kang, Deok Lae Ahn, Jae Geun Oh, Won Ki Joo, Su-Jin Chae
  • Publication number: 20210313470
    Abstract: An oxide semiconductor thin film transistor and a method of forming the oxide semiconductor thin film transistor are provided. The oxide semiconductor thin film transistor can include a semiconductor layer including a channel region, a source region and a drain region; a first gate insulating layer on the semiconductor layer; a gate electrode on the first gate insulating layer; a second gate insulating layer on the gate electrode; an auxiliary electrode on the second gate insulating layer; an interlayer insulating layer on the auxiliary electrode; and a source electrode and a drain electrode on the interlayer insulating layer, wherein the source region and the drain region being disposed at both sides of the channel region, wherein the gate electrode overlapping with the channel region, and the auxiliary electrode overlapping with the gate electrode.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 7, 2021
    Applicant: LG Display Co., Ltd.
    Inventors: Hyuk JI, Jin Chae JEON, Jae Hyun KIM, Sun Young CHOI, Mi Jin JEONG
  • Patent number: 11135223
    Abstract: The present invention provides compositions and methods for inhibiting Dkk-1 for treating or preventing an inflammatory or inflammatory-related disease or disorder.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 5, 2021
    Assignee: Yale University
    Inventors: Wook-Jin Chae, Alfred Bothwell
  • Publication number: 20200373353
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.
    Type: Application
    Filed: December 11, 2019
    Publication date: November 26, 2020
    Inventors: Chi-Ho KIM, Min-Seon KANG, Hyun-Seok KANG, Hyo-June KIM, Jae-Geun OH, Su-Jin CHAE
  • Publication number: 20200203361
    Abstract: A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.
    Type: Application
    Filed: August 27, 2019
    Publication date: June 25, 2020
    Inventors: Dae Gun KANG, Hyun Seok KANG, Deok Lae AHN, Jae Geun OH, Won Ki JOO, Su-Jin CHAE
  • Publication number: 20200108584
    Abstract: Provided are a graphene-based laminate, a method of preparing the same, and a transparent electrode and an electronic device each including the graphene-based laminate. The graphene-based laminate includes a substrate, a graphene layer including graphene and disposed on at least one surface of the substrate, and a metal oxide layer disposed on at least one surface of the graphene layer, wherein the metal oxide layer includes a metal oxide having a greater work function than that of the graphene, and the metal oxide layer includes the metal oxide in an amount of 1 ?g to 1 mg per unit area of 1 cm2 of the graphene layer.
    Type: Application
    Filed: January 31, 2019
    Publication date: April 9, 2020
    Applicant: HANWHA AEROSPACE CO.,LTD
    Inventors: Sunae SEO, Somyeong SHIN, Jin Sung PARK, Jong Hyuk YOON, Jin Ho JANG, Seung Jin CHAE
  • Patent number: 10547001
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Dae-Gun Kang, Su-Jin Chae, Sung-Kyu Min, Myoung-Sub Kim, Chi-Ho Kim, Su-Yeon Lee
  • Patent number: 10489000
    Abstract: A digitizer in which a touch sensing electrode of a self-capacitive type touch sensor and a first electrode of the digitizer are formed on the same layer is provided. The digitizer according to the present invention has a high level of pressure sensing and a simplified manufacturing process.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: November 26, 2019
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Seung Jin Chae, Yoonho Huh, Byung Jin Choi
  • Patent number: 10474266
    Abstract: A flexible digitizer comprising a flexible substrate and a first and a second electrodes having thicknesses of 2000 ? to 1 ?m is provided. The digitizer according to the present invention has sufficient flex resistance for application to a flexible display device with superior electrical characteristics and visibility.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: November 12, 2019
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Seung Jin Chae, Yoonho Huh, Byung Jin Choi
  • Publication number: 20190085092
    Abstract: The invention provides improved compositions for adoptive cell therapies for cancers that express the glycoepitope STn on TAG-72.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 21, 2019
    Applicants: bluebird bio, Inc., ViroMed Co., LTD.
    Inventors: Richard MORGAN, Kevin FRIEDMAN, Seung Shin YU, Jae-Gyun JEONG, Jin-A CHAE
  • Publication number: 20190067064
    Abstract: Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.
    Type: Application
    Filed: August 29, 2018
    Publication date: February 28, 2019
    Inventors: Sunna Chang, Ryan Park, Jin Chae, Matthew Whitlock, Jonathan Lie, Athens Okoren
  • Publication number: 20190067062
    Abstract: Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.
    Type: Application
    Filed: August 29, 2018
    Publication date: February 28, 2019
    Inventors: Sunna Chang, Ryan Park, Jin Chae, Matthew Whitlock, Jonathan Lie, Athens Okoren
  • Publication number: 20190022094
    Abstract: The present invention provides compositions and methods for inhibiting Dkk-1 for treating or preventing an inflammatory or inflammatory-related disease or disorder.
    Type: Application
    Filed: January 20, 2017
    Publication date: January 24, 2019
    Inventors: Wook-Jin Chae, Alfred Bothwell
  • Publication number: 20180358556
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.
    Type: Application
    Filed: January 23, 2018
    Publication date: December 13, 2018
    Inventors: Dae-Gun KANG, Su-Jin CHAE, Sung-Kyu MIN, Myoung-Sub KIM, Chi-Ho KIM, Su-Yeon LEE
  • Publication number: 20180335695
    Abstract: Disclosed herein are a photosensitive resin composition and an organic insulating film prepared therefrom. By optimizing the weight average molecular weight of an alkali-soluble resin and the amount of each component in the photosensitive resin composition, a coated film obtained therefrom may have high planarity property and patterns with high resolution. Accordingly, the photosensitive resin composition may be used as a material for an organic insulating film simultaneously functioning as white pixels in a liquid crystal display.
    Type: Application
    Filed: October 4, 2016
    Publication date: November 22, 2018
    Inventors: Yu-Jin Chae, Ju-Young Jung, Seung-Ho Kwon, Jung-Hwa Lee, Seung-Keun Kim