Abstract: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.

Abstract: Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.

Abstract: A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer.

Abstract: Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip comprising a chip pad, and a rerouting layer disposed on the semiconductor chip and including a metal interconnection electrically connected to the chip pad and a partial oxidation region formed by the oxidation of metal and insulating the metal interconnection.

Abstract: A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units.

Abstract: Disclosed herein are a package substrate and a method of fabricating the same. The package substrate includes a base part that includes a chip, a mold part surrounding the chip, and a connection unit formed inside the mold part to connect the chip to a terminal part formed on the outer surface of the mold part, and a buildup layer that is formed on one surface of the base part on which the terminal part is formed, including the side surfaces of the base part, but includes a circuit layer connected to the terminal part, thereby making it possible to minimize stress applied to chips during a buildup process and easily replace malfunctioning chips.

Abstract: A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.

Abstract: The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.

Abstract: Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.

Abstract: This invention relates to a fly reel, of which the drag system installed in the frame thereof comprises: a drag knob that is connected rotational to one side of periphery of the center shaft that is connected fixed to hub of frame; a drag disk that is spaced-apart from said drag knob and gets inserted rotational to periphery of said center shaft; a braking means for restraining said drag disk from rotating on said center shaft in accordance with transferred amount of said drag knob moved to axial direction of said center shaft; a drag disk bush that is inserted at said drag disk for being rotated together with said drag disk as said drag disk rotates, the drag disk bush having said center shaft inserted therein; a oneway bearing that is inserted at periphery of said drag disk bush, for permitting one directional rotation but for restraining the other directional rotation; and a drag cover that is inserted rotational at periphery of said center shaft so as to be rotated by regulated rotation of said spool, for

Abstract: The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.

Abstract: The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips.

Abstract: The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.

Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

Abstract: This invention relates to a fly reel, of which the drag system installed in the frame thereof comprises: a drag knob that is connected rotational to one side of periphery of the center shaft that is connected fixed to hub of frame; a drag disk that is spaced-apart from said drag knob and gets inserted rotational to periphery of said center shaft; a braking means for restraining said drag disk from rotating on said center shaft in accordance with transferred amount of said drag knob moved to axial direction of said center shaft; a drag disk bush that is inserted at said drag disk for being rotated together with said drag disk as said drag disk rotates, the drag disk bush having said center shaft inserted therein; a oneway bearing that is inserted at periphery of said drag disk bush, for permitting one directional rotation but for restraining the other directional rotation; and a drag cover that is inserted rotational at periphery of said center shaft so as to be rotated by regulated rotation of said spool, for

Abstract: A method for managing downloads of contents. This method provides for a replay memory that stores a globally unique right object identifier (GUID) and a right issuer timestamp (RITS). A duplication memory is used to store a right object (RO) in downloading a duplicate of content that is already stored in the replay memory. When a right issuer timestamp (RITS) included in the right object (RO) of the currently received content is less than the current time plus the set threshold value, and the globally unique right object identifier (GUID) and the right issuer timestamp (RITS) of the received right object (RO) are already stored in the replay memory, the received right object (RO) is separately stored in the duplication memory in association with the globally unique right object identifier (GUID).

Abstract: A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

Abstract: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.

Abstract: A method for managing download of contents includes: providing a replay memory for storing a globally unique right object identifier (GUID) and a right issuer timestamp (RITS), and a duplication memory for storing a right object (RO) in downloading a duplicate of content that is already stored in the replay memory; when a right issuer timestamp (RITS) included in the right object (RO) of the currently received content is less than the current time plus the set threshold value, and the globally unique right object identifier (GUID) and the right issuer timestamp (RITS) of the received right object (RO) are already stored in the replay memory, separately storing the received right object (RO) in the duplication memory in association with the globally unique right object identifier (GUID); and when a content usage right is determined to expire based on the globally unique right object identifier (GUID) and the right issuer timestamp (RITS) which are already stored in the replay memory, continuously providing the

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.