Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

Abstract: A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

Abstract: There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.

Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

Abstract: An atomic layer deposition (ALD) apparatus includes a first process chamber in which a substrate is accommodated, a plasma generating unit provided on the outside of the first process chamber, a source gas supply unit provided on an upper portion of the plasma generating unit, and configured to supply a plurality of source gases, a purge gas supply unit configured to supply a purge gas to the first process chamber, and a gas control unit configured to control the supply of the source gases and the purge gas, wherein the plasma generating unit includes a second process chamber providing a space in which plasma is generated and a plasma antenna inducing a magnetic field in the second process chamber, and the source gases are supplied to the first process chamber through the plasma generating unit.

Abstract: There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.

Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

Abstract: There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.

Abstract: According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

Abstract: In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.

Abstract: A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.

Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.

Abstract: A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

Abstract: Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

Abstract: A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.

Abstract: An indoor unit of an air conditioner has an improved discharge structure of air. The indoor unit of an air conditioner includes a panel which defines an external appearance thereof and has an opening, a mixed flow fan which is located within the panel, a heat exchanger unit which is located rearward of the mixed flow fan, an inlet port which is located rearward of the heat exchanger unit so that air is suctioned from rearward of the heat exchanger unit to be introduced into the mixed flow fan, an outlet port which is exposed forward of the panel through the opening so that the air passing though the mixed flow fan is discharged through a front portion of the panel, and a plurality of circular louvers to open and close the outlet port by moving outwards from a center of the outlet port.

Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.