Patents by Inventor Jin-Gyun Kim

Jin-Gyun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120001264
    Abstract: Provided according to embodiments of the present invention are methods of fabricating semiconductor devices using an etchant. In some embodiments, the etchant may be highly selective and may act to reduce interference between wordlines in the semiconductor device. In some embodiments of the invention, provided are methods of fabricating a semiconductor device that include forming a plurality of gate patterns on a substrate; forming first insulation layers between the gate patterns; wet-etching the first insulation layers to form first insulation layer residues; and forming air gaps between the plurality of gate patterns. Related etchant solutions and semiconductor devices are also provided.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 5, 2012
    Inventors: Hong-suk Kim, Jin-gyun Kim, Hun-Hyeong Lim, Ki-hyun Hwang, Jae-Young Ahn, Jun-kyu Yang
  • Publication number: 20110306195
    Abstract: In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.
    Type: Application
    Filed: May 3, 2011
    Publication date: December 15, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Gyun Kim, Bo-Young Lee, Ki-Hyun Hwang, Eunkee Hong, Jong-Wan Choi
  • Publication number: 20110303970
    Abstract: A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.
    Type: Application
    Filed: May 10, 2011
    Publication date: December 15, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Gyun Kim, Myoung-Bum Lee
  • Publication number: 20110045667
    Abstract: A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction gas having trisilane (Si3H8) and formed on the first conductive layer pattern, and a second conductive layer pattern including metal silicide and formed on the diffusion preventing layer pattern. Since a gate of PMOS transistor includes a diffusion preventing layer having an excellent surface morphology, diffusion of impurities is sufficiently prevented. Thus, the threshold voltage of PMOS transistor may be reduced and threshold voltage distribution may be improved.
    Type: Application
    Filed: October 28, 2010
    Publication date: February 24, 2011
    Inventors: Jin-Gyun Kim, Ki-Hyun Hwang, Sang-Ryol Yang
  • Patent number: 7846836
    Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kak Lee, Ki-Hyun Hwang, Jin-Gyun Kim
  • Publication number: 20100248457
    Abstract: Provided is a method of forming a nonvolatile memory device. The method may include alternatingly stacking n number of dielectric layers and n number of conductive layers on a substrate, forming a non-photosensitive pattern on the alternatingly stacked dielectric layers and conductive layers, etching the i-th conductive layer and i-th dielectric (2?i?n, i is a natural number indicating a stacking order of the conductive layers and the dielectric layers) by using the non-photosensitive pattern as an etch mask, laterally etching a sidewall of the non-photosensitive pattern and etching the i-th conductive layer, (i?1)-th conductive layer, i-th dielectric layer and (i?1)-th dielectric layer by using the etched non-photosensitive pattern as an etch mask.
    Type: Application
    Filed: March 17, 2010
    Publication date: September 30, 2010
    Inventors: SEUNGMOK SHIN, Soodoo Chae, Jin Gyun Kim
  • Patent number: 7763542
    Abstract: A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of fabricating the semiconductor memory device is also provided.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: July 27, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Ki-Sun Kim, Jae-Young Ahn
  • Patent number: 7759192
    Abstract: A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and a doped polysilicon layer epitaxially deposited on the doped poly-Si1-xGex layer and the contact plug makes a contact with the doped polysilicon layer.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Young Ahn, Jin-Tae Noh, Hee-Seok Kim, Jin-Gyun Kim, Ju-Wan Lim, Sang-Ryol Yang, Hong-Suk Kim, Sung-Hae Lee
  • Patent number: 7622383
    Abstract: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: November 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Ki-Hyun Hwang, Jin-Tae Noh, Hong-Suk Kim, Sung-Hae Lee
  • Publication number: 20090280615
    Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.
    Type: Application
    Filed: May 4, 2009
    Publication date: November 12, 2009
    Inventors: Dong-Kak LEE, Ki-Hyun HWANG, Jin-Gyun KIM
  • Publication number: 20090042383
    Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.
    Type: Application
    Filed: July 28, 2008
    Publication date: February 12, 2009
    Inventors: JIN GYUN KIM, Bon-young Koo, Ki-hyun Hwang
  • Patent number: 7488694
    Abstract: The present invention provides nitrogenous compositions for forming a silicon nitride layer, wherein the nitrogenous composition comprises a hydrazine compound, an amine compound or a mixture thereof. The present invention further provides source compositions for forming a silicon nitride layer, wherein the source composition comprises a nitrogenous composition comprising a hydrazine compound, an amine compound or a mixture thereof, and a silicon source comprising hexachlorodisilane. Methods for forming silicon nitride layers are further provided. The silicon nitride layers provided herein may be formed on a substrate at a low temperature and may further exhibit improved breakdown voltage and an enhanced etch resistance.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: February 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Jae-Young Ahn, Hee-Seok Kim, Ju-Wan Lim
  • Publication number: 20080048277
    Abstract: A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction gas having trisilane (Si3H8) and formed on the first conductive layer pattern, and a second conductive layer pattern including metal silicide and formed on the diffusion preventing layer pattern. Since a gate of PMOS transistor includes a diffusion preventing layer having an excellent surface morphology, diffusion of impurities is sufficiently prevented. Thus, the threshold voltage of PMOS transistor may be reduced and threshold voltage distribution may be improved.
    Type: Application
    Filed: August 21, 2007
    Publication date: February 28, 2008
    Inventors: Jin-Gyun Kim, Ki-Hyun Hwang, Sang-Ryol Yang
  • Publication number: 20070134415
    Abstract: An oxidation treatment apparatus for oxidizing a surface of a substrate includes a process chamber for performing a process, a boat supporting the substrate and disposed in the process chamber during the process and a first ozone supply unit supplying ozone to the process chamber. The first ozone supply unit includes an ozone generator disposed at an exterior of the process chamber and an ozone spray nozzle disposed in the process chamber to spray the ozone supplied from the ozone generator into the process chamber.
    Type: Application
    Filed: November 28, 2006
    Publication date: June 14, 2007
    Inventors: Ki-Hyun Hwang, U-In Chung, Yu-Gyun Shin, Jae-Young Ahn, Jin-Gyun Kim
  • Publication number: 20070111545
    Abstract: Provided herein are methods of forming a silicon dioxide layer on a substrate using an atomic layer deposition (ALD) method that include supplying a Si precursor to the substrate and forming on the substrate a Si layer including at least one Si atomic layer; and (b) supplying an oxygen radical to the Si layer to replace at least one Si—Si bond within the Si layer with a Si—O bond, thereby oxidizing the Si layer, to form a silicon dioxide layer on the substrate.
    Type: Application
    Filed: September 14, 2006
    Publication date: May 17, 2007
    Inventors: Sung-hae Lee, Ki-hyun Hwang, Jin-gyun Kim, Sang-ryol Yang, Hong-suk Kim, Jin-tae Noh
  • Publication number: 20070082492
    Abstract: A semiconductor memory device includes a semiconductor substrate. An inter-layer dielectric is disposed on the semiconductor substrate. A bit line is disposed on the inter-layer dielectric. A bit line spacer is fabricated of a nitride layer containing boron and/or carbon and covers sidewalls of the bit line. A method of fabricating the semiconductor memory device is also provided.
    Type: Application
    Filed: August 16, 2006
    Publication date: April 12, 2007
    Inventors: Jin-Gyun Kim, Ki-Sun Kim, Jae-Young Ahn
  • Publication number: 20070042548
    Abstract: A method of forming a silicon layer on a substrate includes providing a silicon source gas to form an amorphous silicon layer on a substrate and providing a dopant source gas to adsorb dopants onto the amorphous silicon layer to form a dopant layer on a surface of the amorphous silicon layer. Related floating gates are also disclosed.
    Type: Application
    Filed: July 31, 2006
    Publication date: February 22, 2007
    Inventors: Jin-Tae Noh, Ki-Hyun Hwang, Jae-Young Ahn, Jin-Gyun Kim, Sang-Ryol Yang
  • Publication number: 20070042573
    Abstract: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.
    Type: Application
    Filed: May 31, 2006
    Publication date: February 22, 2007
    Inventors: Jin-Gyun Kim, Ki-Hyun Hwang, Jin-Tae Noh, Hong-Suk Kim, Sung-Hae Lee
  • Patent number: 7176533
    Abstract: Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: February 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Ae Chung, Myoung-Bum Lee, Young-Pil Kim, Jin-Gyun Kim, Bean-Jun Jin
  • Publication number: 20070023815
    Abstract: A non-volatile memory device comprises a floating gate formed across an active region of a semiconductor substrate, and a control gate electrode formed over the floating gate. An insulation pattern is formed between the floating gate and the active region such that the insulation pattern makes contact with a bottom edge and a sidewall of the floating gate.
    Type: Application
    Filed: July 27, 2006
    Publication date: February 1, 2007
    Inventors: Dong-Yean Oh, Jeong-Hyuk Choi, Jai-Hyuk Song, Jong-Kwang Lim, Jae-Young Ahn, Ki-Hyun Hwang, Jin-Gyun Kim, Hong-Suk Kim