Abstract: A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.

Abstract: A semiconductor memory device includes a cell area; a predetermined cell block table for outputting the logical cell block address and the candidate information; and a tag block for receiving a row address, sensing a logical cell block address in the row address and outputting a physical cell block address based on the logical cell block address and the candidate information, wherein the tag block includes: a N+1 number of unit tag tables, each having M number of registers and storing a store information that the registers corresponds to M number of word lines, each register storing each the physical unit cell block address in response to the logical cell block among unit cell block addresses having a word line in response to the candidate information; and an initialization unit for initializing the N+1 number of unit tag tables.

Abstract: A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

Abstract: Circuit for reducing a standby current, is disclosed, including a PMOS transistor connected to a power supply voltage terminal, an NMOS transistor connected to a ground voltage terminal, and a switching device between the PMOS transistor and the NMOS transistor for cutting off a leakage current flowing to the NMOS transistor through the PMOS transistor, whereby minimizing a leakage current and shortening a time period for going from a standby state to an active state.

Abstract: A delay time compensation circuit for a clock buffer includes first and second toggle flip-flops multiplying an input clock signal and a delay clock signal which is delayed by an input buffer, respectively, a time interval extraction chain extracting a time interval between a rising edge of the input clock signal and a rising edge of the delay clock signal in accordance with clock signals multiplied in the first and second toggle flip-flops, and a variable delay chain delaying the input clock signal by a time interval extracted from the time interval extraction chain. The circuit employs a ½ multiplied clock signal and operates without regard to a duty cycle of an input clock signal, thereby compensating for all the delay time within the cycle of the input clock signal.

Abstract: A circuit for reading data from a memory device reduces electric power consumption by recycling in a precharge period the charge consumed in a preceding sensing period. The circuit includes a pair of data lines set to a voltage level higher than a precharge voltage by the sensing operation of a pull-up amplifier, and a pair of data lines set to a voltage level lower than the precharge voltage by the sensing operation of a pull-down amplifier. The charge consumed in the sensing period is recycled by electrically connecting the two pairs of data lines, respectively, during a succeeding precharge period.

Abstract: An address signal transition detecting apparatus includes an address transition detecting circuit for detecting transitions in address signals, accordingly generating address transition detection signals and summing the address transition detection signals to generate an address transition detection sum signal ATDSUM, respectively outputting a first pulse signal YE for activating a column address decoder, a second pulse signal P for activating a precharger and a third pulse signal SE for activating a sense amplifier in accordance with an address transition detecting sum signal ATDSUM, and once again outputting another first pulse signal YE for activating the column address decoder in response to a fourth pulse signal YE2 generated in accordance with the address transition detection sum signal ATDSUM and the first pulse signal YE.

Abstract: An improved cell array and sense amplifier structure and embodied method are disclosed. The structure exhibits an improved noise characteristic by decreasing a coupling noise which occurs between bit lines by using, as a reference bit line, a bit line from an array of memory cells other than the array to which the bit line belongs, thus forming a predetermined spacing between a bit line and a reference bit line. The structure includes: an upper sense amplifier having an input terminal commonly connected with a first pair of bit lines of an adjacent first cell array and another input terminal commonly connected with a first pair of bit lines of a non-adjacent second cell array; and a lower sense amplifier having an input terminal commonly connected with a second pair of bit lines of the second cell array and another input terminal connected with a second pair of bit lines of the first cell array.

Abstract: A hierarchical word line structure for a semiconductor memory is provided that substantially eliminates coupling noise between neighboring wiring lines by driving neighboring sub-word lines by different main word lines. The hierarchical word line structure further reduces a layout size. The hierarchical word line structure uses one less transistor than a related art sub-word line driver. The word line includes a plurality of word line rows that each include a plurality of sub-word line drivers. The sub-word line drivers receive sub-word line driver enable signals among which only one signal becomes high level at a time. Each of the word line rows correspond to a main word line and a subset of the plurality of sub-word line drivers that drive neighboring sub-word lines are coupled to different respective main word lines.

Abstract: A drive signal generating circuit for a sense amplifier compatible with a semiconductor memory device by driving a sense amplifier using both voltage applied from the outside and voltage outputted from a voltage generator. In a conventional circuit, when operating voltage of a sense amplifier is lowered, it is difficult to operate the sense amplifier in high speed as efficiency is lowered. Further, when only using output voltage outputted from the voltage generator, refresh characteristic of the memory cell is lowered because load is great and the sense amplifier is unstably operated in initial sensing state.

Abstract: A memory device has a page copy mode that writes data into memory cell by memory page units by using a common bit line without outputting accessed data externally. The memory device, e.g., a DRAM includes an interface unit having an address multiplexor for multiplexing a plurality of address signal bits in accordance with a row address strobe signal. A row address resetting unit is for resetting an output signal from the address multiplexor in accordance with the row address strobe signal. A pre-decoder decodes an output signal from the row address resetting unit. A row decoder is for decoding an output signal from the pre-decoder. A word line driving unit receives an output signal from the row decoder to drive a corresponding word line. A block decoding signal latch unit latches an output signal from the pre-decoder in accordance with a page copy signal.

Abstract: A drive signal generating circuit for a sense amplifier compatible with a semiconductor memory device by driving a sense amplifier using both voltage applied from the outside and voltage outputted from a voltage generator. In a conventional circuit, when operating voltage of a sense amplifier is lowered, it is difficult to operate the sense amplifier in high speed as efficiency is lowered. Further, when only using output voltage outputted from the voltage generator, refresh characteristic of the memory cell is lowered because load is great and the sense amplifier is unstably operated in initial sensing state.

Abstract: An improved memory driving method for a semiconductor memory apparatus capable of achieving a series of data accesses by connecting two sense amplifying units to a pair of bit lines, which includes the steps of a first step which senses a data of a memory cell selected by a word line driver and stores the thusly sensed data into a first sense amplifying unit in accordance with a switching operation of a first switch; a second step which selects another memory cell during a sensing operation of the first sense amplifying unit and stores a data of the memory cell into a second sense amplifying unit in accordance with a switching operation of a second switch; and a third step which records data stored in the first sense amplifying unit and second sense amplifying unit into selected memory cells, respectively, in accordance with a certain line and a switch signal, so that data access time of the system can be advantageously reduced.

Abstract: A bit line structure is disclosed.

Abstract: A bit line structure is disclosed.

Abstract: A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections.