Abstract: A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar; a first second-type well including a first sense amplifying MOS transistor having a first-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar.

Abstract: A semiconductor memory device maintains a same operation speed, without a use of high voltage, even when a driving voltage is low (e.g., below 1.0V). In particular, the inventive semiconductor memory device can reduce a leakage current in a bit line sense amp unit at a low voltage.

Abstract: A data latch circuit for latching a data and a method for latching a data signal in synchronization with a clock signal are provided. The data latch circuit includes: a data input controller for outputting a first data transition detection signal in response to a first transition point of the data signal, and outputting a second data transition detection signal in response to a second transition point of the data signal; and a data latch unit for starting latching the data signal in response to the first data transition detection signal and finishing latching the data signal in response to the second data transition detection signal, wherein the data latch unit deactivates the first data transition detection signal corresponding to the start of latching the data signal, and outputs a feedback signal for deactivating the second data transition detection signal corresponding to the finish of latching the data signal.

Abstract: A unit memory cell for use in a pseudo static random access memory (SRAM) includes a cell capacitor; a normal accessing transistor whose gate, drain and source are respectively connected to a normal accessing word line, a normal accessing bit line and a storage node of the cell capacitor; and a refresh accessing transistor whose gate, drain and source are respectively connected to a refresh accessing word line, a refresh accessing bit line and the storage node of the cell capacitor.

Abstract: A semiconductor memory device includes a first cell block having a plurality of unit cells for providing a data signal included in a unit cell through a corresponding bit line pair; a plurality of bit line sense amplifying blocks for sensing and amplifying the data signal delivered to the corresponding bit line pair by using the power supply voltage and a low voltage which is lower than the ground voltage; a decoding unit for generating a plurality of decoding signals to provide the plurality of decoding signals into the plurality of bit line sense amplifying blocks respectively in order to deliver the sensed and amplified data signal to a data line; and a low voltage generation unit for generating the low voltage by using a parasitic capacitor generated at a signal line of the decoding signal as a storing capacitor.

Abstract: A data input buffer in a semiconductor is capable of avoiding operation speed deterioration of the data input buffer due to the temperature condition or process characteristic. The data input buffer in a semiconductor device includes an input detecting unit for detecting logic level of input data by comparing the voltage level of the input data with a reference voltage, a current driving capability adjusting unit for adjusting current driving capability of the input detecting unit based on at least one of temperature condition and process characteristic, and a buffering unit for buffering the output signal from the input detecting unit.

Abstract: A data latch circuit for latching a data signal in synchronization with a clock signal includes a hold time delay unit for generating a first clock signal by delaying the clock signal for a hold time of the data signal and an inverse first clock signal as a second clock signal; a data input control unit for generating a first data transition detection signal in response to the first clock signal and a first transition timing of the data signal and a second data transition detection signal in response to the second clock signal and a second transition timing of the data signal; and a data latch unit for starting latching the data signal in response to the first data transition detection signal and finishing the latching of the data signal in response to the second data transition detection signal.

Abstract: A semiconductor device for improving an operation speed of a data input buffer includes: a plurality of data input buffers each for detecting a logic level of an input data by comparing the input data with a reference voltage to output the detected signal as an internal data signal; and a base voltage driving unit for driving a base power supply terminal of each data input buffer with one of a ground voltage and a negative boosted voltage according to an operation mode.

Abstract: There are provided an output driver for a semiconductor device for securing the constant pull-up and pull-down drivability regardless of temperature condition and process characteristic. The output driver for a semiconductor device includes a first driving unit for transmitting an output data; a detecting unit for detecting at least one of a temperature condition and a process characteristic; an auxiliary pull-up driving unit for pulling up a level of the output data in response to the detection result of the detecting unit; and an auxiliary pull-down driving unit for pulling down the level of the output data in response to the detection result of the detecting unit.

Abstract: A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data from the global data line to the local data line pair; and an input/output (I/O) switching unit for transferring the read data from a segment data line pair to the local data line pair and for transferring the write data from the local data line pair to the segment data line pair, wherein each of the local data line pair and the segment line pair includes a VDD precharge block.

Abstract: The present invention provides a semiconductor design technology, in particular a data input buffer for use therein. This data input buffer secures a data level sensing margin in a weak data transmission cycle upon an asymmetrical data pattern transmission. Specifically, the present invention provides a technology of improving a level sensing margin in a weak data transmission cycle following after adjusting a reference level for input sensing by a constant level toward a strong data direction in a strong data transmission cycle (in case of repeating data with same polarity) by tracing a pattern of transmission data. Further, the present invention employs a method of adjusting an amount of current that flows in a data input part and a reference voltage input part to make a pull-up/pull-down of the reference level without a change of the reference voltage that is constant voltage.

Abstract: An output driver of a semiconductor device, removing the inter-symbol interference noise in data transmission in order to achieve a signal integrity, includes a main driver for driving an output terminal and a supporting driver for controlling the inter-symbol interference noise. The supporting driver is provided with a pull up supporting driver for pulling up the output terminal by detecting a transmission pattern of an output data and a pull down supporting driver for pulling down the output terminal by detecting the transmission pattern of the output data.

Abstract: A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.

Abstract: A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.

Abstract: A semiconductor memory device having a high speed for a data transmission includes a plurality of cell blocks, each having a plurality of unit cells for storing data; a plurality of local bit line sense amplifying block, each for sensing and amplifying the data stored in the N number of cell blocks; a global bit line sense amplifying block for latching the data amplified by the local bit line sense amplifying blocks; and a data transferring block for transmitting the data from the local bit line sense amplifying block to the global bit line sense amplifying block.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; and a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference transistor for connecting a first terminal of the reference capacitor to the bit line, a second reference transistor for connecting the first terminal of the reference capacitor to the bit line bar, and a third reference transistor connected to a reference voltage for supplying the reference voltage to the first terminal of the reference capacitor.

Abstract: A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference metal oxide semiconductor (MOS) transistor for connecting the reference capacitor to the bit line, and a second reference MOS transistor for connecting the reference capacitor to the bit line bar; and a third reference MOS transistor coupled to the reference cell block for charging the reference capacitor with a reference voltage.

Abstract: A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.

Abstract: A semiconductor memory device for outputting or storing a data in response to inputted address and command includes a first cell array for outputting the data to one of a bit line and a bit line bar; a first reference cell block for outputting a reference signal to the other of the bit line and the bit line bar; a sense amplifying block for sensing and amplifying a voltage difference between the bit line and the bit line bar; and a floating control block for floating the bit line and the bit line bar if a precharge command signal is activated.