Abstract: Disclosed are a nitride-based semiconductor device and a method of manufacturing the same. The device has improved frequency characteristics because it has a shorter gate length than existing devices. The shorter gate length can be obtained without using a high-performance patterning device or technology using the patterning device.

Abstract: An RF switch device and a method of manufacturing the same are proposed. A trap area is formed in or on a surface of a highly resistive substrate to trap carriers accumulating on the surface of the substrate, thus improving RF characteristics.

Abstract: Disclosed is an RF switch device and, more particularly, an RF switch device having an air gap over a gate electrode and a metal interconnect at a position higher than the air gap and that at least partially overlap the air gap in the vertical direction, thereby preventing exposure of an upper portion of the air gap in subsequent processing.

Abstract: Provided is an RF switch device and a method of manufacturing the same and, more particularly, to an RF switch device that improves the on-resistance (Ron) of the RF switch by including an integral or integrally formed P diode. The RF switch device includes a first active region on a first substrate as a first base, a second active region on the first substrate spaced apart from the first active region as a second base, and a gate electrode on the first active region and on the second active region.

Abstract: A semiconductor device is disclosed. The semiconductor device includes impurity regions formed in surface portions of a substrate, gate structures formed on surface portions of the substrate between the impurity regions, a first insulating layer formed on the impurity regions and the gate structures, first wiring patterns formed on the first insulating layer, and first contact patterns connecting the impurity regions and the first wiring patterns through the first insulating layer, and the first wiring patterns are arranged in a zigzag shape.

Abstract: An RF switch device and a method of manufacturing the same are proposed. A trap area is formed in or on a surface of a highly resistive substrate to trap carriers accumulating on the surface of the substrate, thus improving RF characteristics.

Abstract: Provided is an RF switch device and a method of manufacturing the same and, more particularly, to an RF switch device and a method of manufacturing the same seeking to improve RF characteristics by forming a trap layer on a part of the surface of a substrate, thereby trapping carriers that may accumulate on the surface of the substrate.

Abstract: Disclosed is an RF switch device and a method of manufacturing the same and, more particularly, an RF switch device and a method of manufacturing the same seeking to improve RF characteristics by forming a trap layer on a part of the surface of a substrate, thereby trapping carriers that may be on the surface of the substrate.

Abstract: An RF switch device and a method of manufacturing the same are disclosed. More particularly, an RF switch device in a stacked configuration and a method of manufacturing the same seeking to reduce or eliminate a voltage imbalance, a condition in which different voltages are applied to different stages of the RF switch device, by forming air gaps on or over corresponding gate electrodes, in which each of the air gaps in a single stage has a different width.

Abstract: Disclosed is an RF switch device and, more particularly, an RF switch device having an air gap over a gate electrode and a metal interconnect at a position higher than the air gap and that at least partially overlap the air gap in the vertical direction, thereby preventing exposure of an upper portion of the air gap in subsequent processing.

Abstract: Provided is an RF switch device (100) in which body contact regions (190) are formed at respective positions adjacent to or partially overlapping opposite ends of a gate region (110) so that holes in a body of the device can escape or flow in either or both of two directions, rather than in only a single direction.

Abstract: A semiconductor device is disclosed. The semiconductor device includes impurity regions formed in surface portions of a substrate, gate structures formed on surface portions of the substrate between the impurity regions, a first insulating layer formed on the impurity regions and the gate structures, first wiring patterns formed on the first insulating layer, and first contact patterns connecting the impurity regions and the first wiring patterns through the first insulating layer, and the first wiring patterns are arranged in a zigzag shape.

Abstract: Provided is an RF switch device (100) in which body contact regions (190) are formed at respective positions adjacent to or partially overlapping opposite ends of a gate region (110) so that holes in a body of the device can escape or flow in either or both of two directions, rather than in only a single direction.

Abstract: A signal control unit for an organic light emitting diode (OLED) display device includes a substrate structure including a plurality of active elements for the pixels, first metal electrodes disposed on the substrate structure, and configured to be electrically connected to a portion of each of the active elements, second metal electrodes disposed over and adjacent the first metal electrodes, configured to electrically connected to corresponding ones of the first metal electrodes, respectively, by via contacts extending vertically to electrically connect the first metal electrodes to the second metal electrodes, and interlayer insulating layer structure interposed between the first electrodes and the second electrodes and having the via contacts therein, the interlayer insulating layer structure having a stacked structure in which a first interlayer insulating layer, a light blocking layer and a second interlayer insulating layer are stacked in order.

Abstract: A signal control unit for an organic light emitting diode (OLED) display device, includes a substrate structure including a plurality of active elements each corresponding to a pixel, a lower metal pattern disposed on the substrate structure, and electrically connected to a portion of the plurality of active elements, an insulating interlayer disposed on the substrate structure and at least partially covering the lower metal pattern, a via contact penetrating through the insulating interlayer and connected to the lower metal pattern, a metal electrode disposed on the insulating interlayer, and connected to the via contact, and an electrode passivation layer pattern substantially covering the metal electrode to expose a center portion of an upper surface of the metal electrode while covering a remainder of the upper surface and a side surface of the metal electrode. Therefore, leakage current which flows through the side surface of the metal electrode is suppressed.

Abstract: An element isolation structure includes a substrate defining a trench including an upper trench and a lower trench in communication with each other, the substrate including an inclined sidewall that forms the upper and lower trench; a first thin film liner on the substrate and conforming to the substrate, the first thin film liner having a substantially uniform thickness trench; a second thin film liner pattern selectively on a lower portion of the first thin film liner within a volume defined by the lower trench, the second thin film liner pattern having a substantially uniform thickness; a lower isolation layer formed on the second thin film liner pattern and substantially filling the volume defined by the lower trench; and an upper isolation layer formed on an upper portion of the first thin film liner and the lower isolation layer and substantially filling a volume defined by the upper trench.

Abstract: A signal control unit for an organic light emitting diode (OLED) display device, includes a substrate structure including a plurality of active elements each corresponding to a pixel, a lower metal pattern disposed on the substrate structure, and electrically connected to a portion of the plurality of active elements, an insulating interlayer disposed on the substrate structure and at least partially covering the lower metal pattern, a via contact penetrating through the insulating interlayer and connected to the lower metal pattern, a metal electrode disposed on the insulating interlayer, and connected to the via contact, and an electrode passivation layer pattern substantially covering the metal electrode to expose a center portion of an upper surface of the metal electrode while covering a remainder of the upper surface and a side surface of the metal electrode. Therefore, leakage current which flows through the side surface of the metal electrode is suppressed.

Abstract: An element isolation structure includes a substrate defining a trench including an upper trench and a lower trench in communication with each other, the substrate including an inclined sidewall that forms the upper and lower trench; a first thin film liner on the substrate and conforming to the substrate, the first thin film liner having a substantially uniform thickness trench; a second thin film liner pattern selectively on a lower portion of the first thin film liner within a volume defined by the lower trench, the second thin film liner pattern having a substantially uniform thickness; a lower isolation layer formed on the second thin film liner pattern and substantially filling the volume defined by the lower trench; and an upper isolation layer formed on an upper portion of the first thin film liner and the lower isolation layer and substantially filling a volume defined by the upper trench.

Abstract: A signal control unit for an organic light emitting diode (OLED) display device includes a substrate structure including a plurality of active elements for the pixels, first metal electrodes disposed on the substrate structure, and configured to be electrically connected to a portion of each of the active elements, second metal electrodes disposed over and adjacent the first metal electrodes, configured to electrically connected to corresponding ones of the first metal electrodes, respectively, by via contacts extending vertically to electrically connect the first metal electrodes to the second metal electrodes, and interlayer insulating layer structure interposed between the first electrodes and the second electrodes and having the via contacts therein, the interlayer insulating layer structure having a stacked structure in which a first interlayer insulating layer, a light blocking layer and a second interlayer insulating layer are stacked in order.

Abstract: In embodiments, a high voltage semiconductor device includes a gate structure disposed on a substrate, a source region disposed at a surface portion of the substrate adjacent to one side of the gate structure, a drift region disposed at a surface portion of the substrate adjacent to another side of the gate structure, a drain region disposed at a surface portion of the drift region spaced from the gate structure, and an electrode structure disposed on the drift region to generate a vertical electric field between the gate structure and the drain region.