Patents by Inventor Jin Hyo Jung
Jin Hyo Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7622764Abstract: Semiconductor devices and a fabricating method therefore are disclosed.Type: GrantFiled: December 30, 2004Date of Patent: November 24, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7605038Abstract: A high voltage semiconductor deice and a manufacturing method thereof are provided. The high voltage semiconductor device comprises: second conductive type drift regions disposed spaced from each other on a first conductive type well region formed on a first conductive type semiconductor substrate; a gate electrode on a channel region between the second conductive type drift regions with a gate insulating film disposed therebetween; second conductive type high-concentration source and drain each disposed in the second conductive type drift regions, spaced from a side of a gate electrode; a gate spacer having a spacer part covering the side of the gate electrode and a spacer extending part to cover a spaced portion of the second conductive type high-concentration source and drain from the side of the gate electrode; and a silicide formed on the gate electrode and the second conductive type high-concentration source and drain.Type: GrantFiled: July 19, 2007Date of Patent: October 20, 2009Assignee: Dongbu Hitek Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7605036Abstract: The method of forming a floating gate array of a flash memory device includes: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the device isolations being formed such that upper portions thereof protrude from a surface of the substrate by a predetermined height; (b) forming tunnel oxide layers in the active device regions; (c) forming a floating gate-forming layer throughout an entire region of the substrate, including regions in which the plurality of device isolations and the active device regions are formed, the floating gate-forming layer being formed such that grooves are formed along the active device regions; (d) filling the grooves formed on the floating gate-forming layer with masking materials; and (e) patterning the floating gate-forming layer, using the masking materials filling the grooves as an etching mask.Type: GrantFiled: December 20, 2006Date of Patent: October 20, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7588986Abstract: According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region, and a logic device region, includes defining the active regions by forming a device isolation region on a semiconductor substrate; performing ion-implantation in the SONOS device region to control a threshold voltage of a SONOS device; performing ion-implantation in the high voltage device region to form a well; performing ion-implantation in the SONOS device region and the logic device region to form a well; and forming an ONO pattern on the SONOS device region, generally by performing a photolithography and etching process on the ONO layer.Type: GrantFiled: December 29, 2005Date of Patent: September 15, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin-Hyo Jung
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Publication number: 20090206382Abstract: A flash memory device and programming and erasing methods therewith is disclosed, to secure the programming and erasing characteristics by changing a structure of a floating gate, in which the flash memory device includes a first conductive type semiconductor substrate defined as a field area and an active area; a tunnel oxide layer on the active area of the first conductive type semiconductor substrate; a floating gate on the tunnel oxide layer, having at least first and second floating gates having different levels of energy band gap; a dielectric layer on the floating gate; a control gate on the dielectric layer; and second conductive type source/drain regions in the active area of the first conductive type semiconductor substrate at both sides of the floating gate.Type: ApplicationFiled: April 15, 2009Publication date: August 20, 2009Inventor: Jin Hyo Jung
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Publication number: 20090209082Abstract: A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.Type: ApplicationFiled: March 27, 2009Publication date: August 20, 2009Inventor: Jin Hyo JUNG
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Publication number: 20090179274Abstract: A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of thType: ApplicationFiled: March 17, 2009Publication date: July 16, 2009Inventor: Jin Hyo JUNG
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Publication number: 20090166717Abstract: Embodiments relate to a nonvolatile memory device and a method for manufacturing the same. According to embodiments, a nonvolatile memory device may include a tunnel ONO film having an oxide film, a nitride film, and an oxide film stacked on and/or over a semiconductor substrate. It may also include a trap nitride film formed on and/or over the tunnel ONO film, a blocking oxide film formed on and/or over the trap nitride film and having a high-dielectric film with a higher dielectric constant than a dielectric constant of a SiO2 film. According to embodiments, a gate may be formed on and/or over the blocking oxide film. An electron back F/N tunneling at the time of an erase operation may be minimized. This may improve an erase speed and erase Vt saturation phenomenon.Type: ApplicationFiled: December 28, 2008Publication date: July 2, 2009Inventor: Jin-Hyo Jung
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Patent number: 7544582Abstract: A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.Type: GrantFiled: August 16, 2005Date of Patent: June 9, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7538378Abstract: A flash memory device and programming and erasing methods therewith is disclosed, to secure the programming and erasing characteristics by changing a structure of a floating gate, in which the flash memory device includes a first conductive type semiconductor substrate defined as a field area and an active area; a tunnel oxide layer on the active area of the first conductive type semiconductor substrate; a floating gate on the tunnel oxide layer, having at least first and second floating gates having different levels of energy band gap; a dielectric layer on the floating gate; a control gate on the dielectric layer; and second conductive type source/drain regions in the active area of the first conductive type semiconductor substrate at both sides of the floating gate.Type: GrantFiled: December 28, 2004Date of Patent: May 26, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7521311Abstract: A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of thType: GrantFiled: May 13, 2005Date of Patent: April 21, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7510936Abstract: Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection gates on the lateral faces of the nitride layer; depositing a first polysilicon, a dielectric layer and a second polysilicon on the surface of the resulting structure, sequentially; patterning the second polysilicon, the dielectric layer and the second polysilicon to form gate electrodes; removing the nitride layer between the injection gates; forming source and drain extension regions around each of the gate electrodes by performing an ion implantation process; forming sidewall spacers on the lateral faces of the gate electrodes; and forming source and drain regions in the substrate by performing an ion implantation process with the sidewall spacers as an ion implantation mask.Type: GrantFiled: August 29, 2007Date of Patent: March 31, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7501319Abstract: A semiconductor device and a fabricating method thereof are disclosed. The semiconductor device includes polysilicon gate electrodes, a gate oxide layer, sidewall floating gates, a block oxide layer, source/drain areas, and sidewall spacers. In addition, the method includes the steps of: forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer; forming sidewall floating gates on lateral faces of the trenches; forming a block oxide layer on the sidewall floating gates; forming polysilicon gate electrodes by a patterning process; removing the sacrificial layer; forming source/drain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and forming spacers on lateral faces of the polysilicon gate electrodes and the sidewall floating gates.Type: GrantFiled: March 30, 2007Date of Patent: March 10, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Patent number: 7482212Abstract: A method of manufacturing a semiconductor device including forming a trench on a first surface of a silicon substrate, forming a thermal oxide layer and a deposited oxide layer on the trench and the silicon substrate, planarizing a second surface of the silicon substrate by a chemical mechanical polishing (CMP) process, and forming a transistor on the second surface of the silicon substrate. The semiconductor device and the method of manufacturing the same provide an SOI device that has low resistance of the source/drain regions and suppress a short channel effect.Type: GrantFiled: December 29, 2005Date of Patent: January 27, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin-Hyo Jung
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Publication number: 20080160706Abstract: A method for fabricating a semiconductor device is provided, in which drift areas are deeply formed in a silicon substrate even when a drive-in process is performed at a relatively lower temperature for a relatively shorter processing time. Therefore, the defects caused by thermal bird's beaks and the horizontal diffusion of implanted impurities can be effectively suppressed. As a result, the punch-through property and the isolation property of high voltage components of the semiconductor device can be improved. Thus, the chip design size can be reduced.Type: ApplicationFiled: December 26, 2007Publication date: July 3, 2008Inventor: Jin Hyo JUNG
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Publication number: 20080160707Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a trench having a predetermined depth in a substrate having an active area and an isolation area by selectively removing the isolation area, forming a well region in the active area of the substrate using the trench as a photo key pattern, forming an isolation layer in the trench by filling the trench with an insulating layer, forming a gate insulating layer on a portion of the well region, forming a gate electrode on the gate insulating layer; and forming a source/drain impurity area on the substrate at both sides of the gate electrode.Type: ApplicationFiled: December 26, 2007Publication date: July 3, 2008Inventor: Jin Hyo JUNG
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Patent number: 7391096Abstract: An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second nitride layer are deposited on the surface of the substrate including the trench. A spacer is formed on the lateral walls of the trench by etching the second nitride layer. A buried oxide is grown in the substrate underneath the trench by performing thermal oxidation on the substrate. The trench is then filled by depositing an insulating layer after removing the spacer and performing a planarization process. The STI fabricating method can reduce substantially a total parasitic capacitance. Therefore, gate RC delay is reduced and the operating speed of a transistor increases.Type: GrantFiled: December 1, 2005Date of Patent: June 24, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung
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Publication number: 20080128790Abstract: A memory device including a region doped with first conductive impurities; a first polysilicon layer doped with second conductive impurities and formed on the region doped with first conductive impurities; a second polysilicon layer formed on the first polysilicon layer and doped with first conductive impurities; an electric charge capture layer formed at a lateral side of the first polysilicon layer; and a control gate formed at a lateral side of the electric charge capture layer.Type: ApplicationFiled: October 9, 2007Publication date: June 5, 2008Inventor: Jin-Hyo Jung
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Publication number: 20080128784Abstract: A flash memory device having a region doped with a first impurity formed on a semiconductor substrate, a first polysilicon pattern having a substantially rectangular configuration formed on and/or over the region; a second polysilicon pattern having a substantially rectangular configuration formed on and/or over the first polysilicon pattern; a plurality of charge trapping layers formed on and/or over sidewalls of the first and second polysilicon patterns; and a plurality of control gates formed on and/or over the charge trapping layers.Type: ApplicationFiled: November 7, 2007Publication date: June 5, 2008Inventor: Jin-Hyo Jung
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Patent number: 7374989Abstract: Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating gate device formed inside the opening; and a select gate device formed on the epitaxial layer at a distance from the floating gate device.Type: GrantFiled: June 26, 2007Date of Patent: May 20, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Jin Hyo Jung