Abstract: An erase method in a flash memory device by which over-erase of the flash memory device is prevented. The method includes applying an electric field to a structure between the control gate and the semiconductor substrate by applying negative and positive voltages to the control gate and the semiconductor substrate, respectively. The method further includes weakening an intensity of the electric field applied to the tunnel oxide layer according to a progress of an erase time, and simultaneously, relatively strengthening an intensity of the electric field applied to the first and second block oxide layers to constantly maintain a prescribed quantity of electrons on a conduction band of the floating gate.

Abstract: Non-volatile memory devices and methods of fabricating the same are disclosed. A disclosed non-volatile memory device includes: a tunnel oxide layer formed on a semiconductor substrate and having an energy bandgap; a storage oxide layer formed on the tunnel oxide layer and having an energy bandgap which is smaller than the energy bandgap of the tunnel oxide layer; a block oxide layer formed on the storage oxide layer and having an energy bandgap greater than the energy bandgap of the storage oxide layer; and a gate formed on the block oxide layer.

Abstract: A non-volatile memory device having sidewall floating gates implementing two bits with just one transistor is disclosed. A disclosed method comprises a non-volatile memory device having a unit cell comprising: a transistor including a polysilicon gate, sidewall floating gates, block oxide layers and source and drain regions; a word line vertically placed on a substrate and connected to the polysilicon gate; and a pair of bit lines orthogonally placed to the word line and connected to the source and drain regions.

Abstract: Methods of fabricating a nonvolatile memory device are disclosed. A disclosed method comprises forming a first buffer oxide layer and a first buffer nitride layer on a semiconductor substrate; forming an opening through the first buffer nitride layer and the first buffer oxide layer; forming sidewall floating gates on sidewalls within the opening; forming a block oxide layer; forming a polysilicon main gate over the sidewall floating gates; forming first sidewall spacers on the sidewalls of the polysilicon main gate and the sidewall floating gates; forming common source and drain regions in the semiconductor substrate; filling the gap between the polysilicon main gates with an insulating layer; depositing a polysilicon layer for a word line; patterning a word line and the polysilicon main gate in the direction of a word line; and forming second sidewall spacers on the sidewalls of the word line and the polysilicon main gate.

Abstract: A fabricating method of a nonvolatile memory device is disclosed. A disclosed method comprises: implanting ions into an active region of a semiconductor substrate to form a well of a low voltage transistor and adjust its threshold voltage; implanting ions into an active region of the semiconductor substrate to form a well of a high voltage transistor and adjust its threshold voltage, thereby forming a conductive region; depositing an ONO layer on the semiconductor substrate; patterning and etching the ONO layer to form an ONO structure; and forming a gate oxide layer on the semiconductor substrate.

Abstract: Methods of forming silicide layers of a semiconductor device are disclosed. A disclosed method comprises depositing a polysilicon layer, a buffer oxide layer, and a buffer nitride layer on a semiconductor substrate; forming a gate on the semiconductor substrate by removing some portion of the polysilicon layer, the buffer oxide layer, and the buffer nitride layer; forming sidewall spacers on the sidewalls of the gate; forming source and drain regions in the semiconductor substrate by performing an ion implantation process; forming a first silicide layer on the source and drain regions; depositing a first ILD layer over the semiconductor substrate including the gate and the first silicide layer; removing some portion of the first ILD layer to expose the top surface of the gate; and forming a second silicide layer on the gate.

Abstract: Non-volatile memory elements having a high programming speed and a reduced constant voltage requirement for data storage. Each memory cell of a non-volatile SRAM includes an SRAM unit and a non-volatile memory unit. When power is off, the data levels of data nodes of the SRAM unit are programmed into a corresponding non-volatile memory element through a pass transistor connected to the data node. When the power is on, the data levels programmed into the non-volatile memory elements are recalled to the corresponding data nodes through the pass transistors, and then the programmed non-volatile memory element is erased. The non-volatile memory element has an oxide stack including a tunnel oxide film, a storage oxide film, and a blocking oxide film. A potential well where the SRAM unit is formed is isolated from a potential well where the non-volatile memory unit is formed. Bias voltages are applied during program, recall and erase modes to the potential well where the non-volatile memory unit is formed.

Abstract: A non-volatile memory including a semiconductor substrate, and a SONOS electrode on the semiconductor substrate, where the SONOS electrode has a channel area defined underneath. The memory also includes a first layer in contact with a side of the SONOS electrode, a second layer in contact with another side of the SONOS electrode, a pass electrode in contact with the first layer, a recall electrode in contact with the second layer, and a pair of doped regions in the semiconductor substrate. The pair of doped regions are formed where the SONOS, pass, and recall electrodes are not formed. The memory further includes a pair of extension channels in the semiconductor substrate under the pass and recall electrodes, where the pair of extension channels extend from the doped regions toward the channel area.

Abstract: An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second nitride layer are deposited on the surface of the substrate including the trench. A spacer is formed on the lateral walls of the trench by etching the second nitride layer. A buried oxide is grown in the substrate underneath the trench by performing thermal oxidation on the substrate. The trench is then filled by depositing an insulating layer after removing the spacer and performing a planarization process. The STI fabricating method can reduce substantially a total parasitic capacitance. Therefore, gate RC delay is reduced and the operating speed of a transistor increases.

Abstract: A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.

Abstract: A non-volatile memory device and a method for driving the same prevent an excessive electron erasing phenomenon without additional components. Each memory cell includes a tunnel oxide layer, a floating gate, a control gate connected to a word line, first and second oxide layers formed between the floating gate and the control gate, and first and second impurity diffusion layers formed in a semiconductor substrate at both sides of the floating gate and connected to a common line and a bit line.

Abstract: A method for fabricating a flash memory includes forming a tunnel oxide layer by depositing a material with a conduction band energy level lower than that of SiO2 on a semiconductor substrate; forming a floating gate by depositing polysilicon on the tunnel oxide layer; forming an intergate dielectric layer on the floating gate; forming a control gate on the intergate dielectric layer; forming a gate electrode by patterning the tunnel oxide layer, the floating gate, the intergate dielectric layer and the control gate; and forming a source/drain region by implanting impurities into the substrate using the gate electrode as a mask.

Abstract: A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a first gate pattern covered with a cap layer on a semiconductor substrate in an active area, and forming an etchant-resistant layer covering one side of the first gate pattern, the etchant-resistant layer extending to a surface of the substrate to cover one confronting side of a neighboring first gate pattern in the active area. The method also includes forming an insulating layer on an exposed surface of the first gate pattern, and forming a second gate pattern covering the first gate pattern and the insulating layer, the second gate pattern not overlapping the etch-resistant layer. The method further includes removing the etch-resistant layer, and forming a pair of doped regions in the substrate aligned with the first and second gate patterns.

Abstract: A flash memory device and programming and erasing methods therewith is disclosed, to secure the programming and erasing characteristics by changing a structure of a floating gate, in which the flash memory device includes a first conductive type semiconductor substrate defined as a field area and an active area; a tunnel oxide layer on the active area of the first conductive type semiconductor substrate; a floating gate on the tunnel oxide layer, having at least first and second floating gates having different levels of energy band gap; a dielectric layer on the floating gate; a control gate on the dielectric layer; and second conductive type source/drain regions in the active area of the first conductive type semiconductor substrate at both sides of the floating gate.

Abstract: A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a dielectric layer on an active area of a semiconductor substrate, forming a first gate covered with a cap layer on the dielectric layer, and forming an insulating layer on a sidewall of the first gate. The method also includes forming a dummy spacer over the sidewall of the first gate, the first gate including the cap layer and the insulating layer, and removing the dielectric layer failing to be covered with the dummy spacer and the dummy spacer to form an exposed portion of the substrate. The method further includes forming a gate insulating layer on the exposed portion of the substrate, and forming a second gate overlapping one side of the first gate, wherein a split gate is configured with the first and second gates.

Abstract: A method of fabricating nonvolatile memory devices. The method includes forming a tunnel oxide layer, a stacked oxide layer, a polysilicon layer for a control gate, a buffer oxide layer and a buffer nitride layer in order on the entire surface of a semiconductor substrate, and patterning the substrate vertically to form a control gate and a first device isolation region. The method also includes implanting ions into the first device isolation region to form common source and drain regions, filling the gap of the first device isolation region to form a first device isolation structure, and removing the buffer nitride layer and the buffer oxide layer. The method further includes depositing polysilicon for a word line on the substrate, and patterning the substrate vertically to form the word line and a second device isolation region, forming sidewall spacers on the sidewalls of the control gate and the word line, and forming silicide on the word line.

Abstract: A non-volatile memory including a semiconductor substrate, and a SONOS electrode on the semiconductor substrate, where the SONOS electrode has a channel area defined underneath. The memory also includes a first layer in contact with a side of the SONOS electrode, a second layer in contact with another side of the SONOS electrode, a pass electrode in contact with the first layer, a recall electrode in contact with the second layer, and a pair of doped regions in the semiconductor substrate. The pair of doped regions are formed where the SONOS, pass, and recall electrodes are not formed. The memory further includes a pair of extension channels in the semiconductor substrate under the pass and recall electrodes, where the pair of extension channels extend from the doped regions toward the channel area.

Abstract: An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second nitride layer are deposited on the surface of the substrate including the trench. A spacer is formed on the lateral walls of the trench by etching the second nitride layer. A buried oxide is grown in the substrate underneath the trench by performing thermal oxidation on the substrate. The trench is then filled by depositing an insulating layer after removing the spacer and performing a planarization process. The STI fabricating method can reduce substantially a total parasitic capacitance. Therefore, gate RC delay is reduced and the operating speed of a transistor increases.