Abstract: A flash memory device and a method of manufacturing the same comprises source and drain diffusion regions formed at fixed intervals in an active area of a silicon semiconductor substrate, charge storage layers of multi-layers formed on the substrate, and a control gate formed on the charge storage layers, wherein the charge storage layers include a tunnel oxide film formed on the silicon semiconductor substrate, and a silicon nitride film formed on the tunnel oxide film, and the silicon nitride film includes a plurality of minute crystals formed by ion-implanting 14-group elements into the silicon nitride film. The flash memory device maintains the good programming and erasing operation of SONOS devices, and also improves trap density and memory window. Because of the difference of energy barrier between the minute crystal and the silicon nitride, the electrons or holes trapped in the minute crystal as the deep trap are not easily detrapped therefrom, thereby improving the data storage property of the device.

Abstract: A flash memory device includes a semiconductor substrate having a field oxide layer defining an active area; a gate oxide layer formed over parts of the active area of the semiconductor substrate; a coupling oxide layer formed over both the semiconductor substrate and a sidewall of the polygate; a floating gate formed over the coupling oxide layer; and a source/drain area formed in an external lower semiconductor substrate of the planar floating gate.

Abstract: Disclosed in a non-volatile (NV) memory device and a method of manufacturing the same. The method includes forming transistor and EEPROM regions by implanting first and second conductive impurity ions into a semiconductor substrate, depositing a gate oxide on an entire surface of the semiconductor substrate, forming a first gate poly on the EEPROM region, removing the gate oxide not below the first gate poly, forming a logic gate oxide, a tunnel oxide and a coupling oxide, forming a logic gate poly on the transistor region and a second gate poly on a sidewall of the first gate poly, forming source/drain extension regions by implanting first and second conductive impurity ions, forming a sidewall spacer on the logic gate poly and the second gate poly, and forming a silicide on the source, drain and logic gate poly of the transistor region.

Abstract: A non-volatile memory device and drive method thereof uses a voltage bias condition to enable an electronic device to normally operate without employing a specific transistor, e.g., a recall transistor. The non-volatile memory device performs its function normally without the recall transistor, and by which a degree of cell integration can be considerably raised. A SRAM latch is controlled by the logic circuit, a SONOS (silicon-oxide-nitride-oxide-silicon) transistor is electrically connected to a Vcc node of the electronic device to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power, and a pass transistor controls read, program, and erase operations of the SONOS transistor.

Abstract: A high voltage semiconductor deice and a manufacturing method thereof are provided. The high voltage semiconductor device comprises: second conductive type drift regions disposed spaced from each other on a first conductive type well region formed on a first conductive type semiconductor substrate; a gate electrode on a channel region between the second conductive type drift regions with a gate insulating film disposed therebetween; second conductive type high-concentration source and drain each disposed in the second conductive type drift regions, spaced from a side of a gate electrode; a gate spacer having a spacer part covering the side of the gate electrode and a spacer extending part to cover a spaced portion of the second conductive type high-concentration source and drain from the side of the gate electrode; and a silicide formed on the gate electrode and the second conductive type high-concentration source and drain.

Abstract: The present invention relates to a MOS transistor which is capable of compensating the shortcomings of the conventional MOS transistor having three gate electrodes. In order to achieve the object the MOS transistor of the present invention is characterized in that the sidewall gates are made of material having an energy band gap higher than that of the material constituting the main gate or the sidewall gates are implanted with holes (or positive charges) or electrons (or negative charges).

Abstract: Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection gates on the lateral faces of the nitride layer; depositing a first polysilicon, a dielectric layer and a second polysilicon on the surface of the resulting structure, sequentially; patterning the second polysilicon, the dielectric layer and the second polysilicon to form gate electrodes; removing the nitride layer between the injection gates; forming source and drain extension regions around each of the gate electrodes by performing an ion implantation process; forming sidewall spacers on the lateral faces of the gate electrodes; and forming source and drain regions in the substrate by performing an ion implantation process with the sidewall spacers as an ion implantation mask.

Abstract: Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating gate device formed inside the opening; and a select gate device formed on the epitaxial layer at a distance from the floating gate device.

Abstract: Non-volatile memory devices and methods for driving the same are disclosed. An example non-volatile memory device includes a semiconductor substrate; source/drain junctions in a predetermined region of the semiconductor substrate; a main gate oxide layer above a surface of the semiconductor substrate and disposed between the source/drain junctions, a first end of the main gate oxide layer comprising a first bit charge storage unit including a first tunnel oxide layer, a first potential well layer, and a first coupling oxide layer, and a second, opposing end of the main gate oxide layer comprising a second bit charge storage unit including a second tunnel oxide layer, a second potential well layer, and a second coupling oxide layer; and a main gate electrode above the main gate oxide layer.

Abstract: A method and non-volatile memory device are provided that are characterized by ion-implantation of impurities in the sidewalls of a first electrode. The inclusion of impurities in the sidewalls eliminates geometric abnormalities, referred to herein as a bird's beak, in the first electrode, which are caused by numerous oxidation processes being performed in the overall memory fabrication process. By eliminating these geometric abnormalities, thickening of the block oxide layer proximate the area of geometric abnormalities does not occurring, resulting in a memory device capable of efficiently programming and erasing data.

Abstract: The method of forming a floating gate array of a flash memory device includes: (a) forming a plurality of device isolations, which define active device regions, in a semiconductor substrate, the device isolations being formed such that upper portions thereof protrude from a surface of the substrate by a predetermined height; (b) forming tunnel oxide layers in the active device regions; (c) forming a floating gate-forming layer throughout an entire region of the substrate, including regions in which the plurality of device isolations and the active device regions are formed, the floating gate-forming layer being formed such that grooves are formed along the active device regions; (d) filling the grooves formed on the floating gate-forming layer with masking materials; and (e) patterning the floating gate-forming layer, using the masking materials filling the grooves as an etching mask.

Abstract: A semiconductor device and a fabricating method thereof are disclosed. The semiconductor device includes polysilicon gate electrodes, a gate oxide layer, sidewall floating gates, a block oxide layer, source/drain areas, and sidewall spacers. In addition, the method includes the steps of: forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer; forming sidewall floating gates on lateral faces of the trenches; forming a block oxide layer on the sidewall floating gates; forming polysilicon gate electrodes by a patterning process; removing the sacrificial layer; forming source/drain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and forming spacers on lateral faces of the polysilicon gate electrodes and the sidewall floating gates.

Abstract: A method of fabricating nonvolatile memory devices. The method includes forming a tunnel oxide layer, a stacked oxide layer, a polysilicon layer for a control gate, a buffer oxide layer and a buffer nitride layer in order on the entire surface of a semiconductor substrate, and patterning the substrate vertically to form a control gate and a first device isolation region. The method also includes implanting ions into the first device isolation region to form common source and drain regions, filling the gap of the first device isolation region to form a first device isolation structure, and removing the buffer nitride layer and the buffer oxide layer. The method further includes depositing polysilicon for a word line on the substrate, and patterning the substrate vertically to form the word line and a second device isolation region, forming sidewall spacers on the sidewalls of the control gate and the word line, and forming silicide on the word line.

Abstract: A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a dielectric layer on an active area of a semiconductor substrate, forming a first gate covered with a cap layer on the dielectric layer, and forming an insulating layer on a sidewall of the first gate. The method also includes forming a dummy spacer over the sidewall of the first gate, the first gate including the cap layer and the insulating layer, and removing the dielectric layer failing to be covered with the dummy spacer and the dummy spacer to form an exposed portion of the substrate. The method further includes forming a gate insulating layer on the exposed portion of the substrate, and forming a second gate overlapping one side of the first gate, wherein a split gate is configured with the first and second gates.

Abstract: The present invention provides a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes: a semiconductor substrate including an active region defined by an isolation layer, having a first conductivity type; a gate formed on the substrate; a first threshold voltage adjusting layer formed on a surface of an active region below the gate, having a second conductivity type; a second threshold voltage adjusting layer formed on a surface of an edge region of the isolation layer, having the first conductivity type; and an insulation layer formed between the gate and the substrate.

Abstract: A method of manufacturing a semiconductor device including forming a trench on a first surface of a silicon substrate, forming a thermal oxide layer and a deposited oxide layer on the trench and the silicon substrate, planarizing a second surface of the silicon substrate by a chemical mechanical polishing (CMP) process, and forming a transistor on the second surface of the silicon substrate. The semiconductor device and the method of manufacturing the same provide an SOI device that has low resistance of the source/drain regions and suppress a short channel effect.

Abstract: According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region, and a logic device region, includes defining the active regions by forming a device isolation region on a semiconductor substrate; performing ion-implantation in the SONOS device region to control a threshold voltage of a SONOS device; performing ion-implantation in the high voltage device region to form a well; performing ion-implantation in the SONOS device region and the logic device region to form a well; and forming an ONO pattern on the SONOS device region, generally by performing a photolithography and etching process on the ONO layer.

Abstract: A non-volatile memory device having a unit cell, the unit cell including a transistor, word lines, a first bit line and a second bit line. The transistor includes a gate oxide layer on a substrate, polysilicon gate, sidewall floating gates, block oxide layers formed between the polysilicon gate and sidewall floating gates, the block oxide layers also comprising first block oxide layer and second block oxide layer, and source and drain regions. The word lines are vertically placed on the substrate and connected to the polysilicon gate. The first bit line is orthogonally placed to the word lines and connected to the source region and a second bit line is orthogonally placed to the word lines and connected to the drain region.

Abstract: A method of fabricating nonvolatile memory devices is disclosed. A nonvolatile memory device comprises: a polysilicon gate on a semiconductor substrate; a gate oxide layer between the polysilicon gate and the substrate; sidewall floating gates on the bottom of the lateral faces of the polysilicon gate; tunnel oxide layers between the sidewall floating gates and the substrate; block oxide layers between the polysilicon gate and the sidewall floating gates; sidewall spacers on the sidewalls of the polysilicon gate and the sidewall floating gates; source and drain extension regions on the substrate under the sidewall spacers; and source and drain regions adjacent to the source and drain extension regions.

Abstract: A method for fabricating a nonvolatile memory device comprises the steps of: defining an active region in a semiconductor substrate; forming a charge trapping layer, a first conducting layer and a capping layer on the active region; patterning the capping layer to form a pair of caps; forming a first conducting pattern having a width defined by the pair of caps; depositing a second conducting layer on the substrate to cover the first conducting pattern; forming a first photoresist pattern on the second conducting layer, the first photoresist pattern having an opening over a portion of the active region between the pair of caps; selectively etching the second conducting layer using the first photoresist pattern as an etch mask, and at the same time selectively etching the first conducting pattern with the pair of caps as an etch mask, to form a pair of first gates.