Patents by Inventor Jin Yim

Jin Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10953593
    Abstract: Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the molding compound are disclosed. The carbon non-tube dispersion has a number of carbon nano-tubes with surfaces that are chemically modified by a functional group to chemically bridge the surfaces of the carbon nano-tubes and the resin, improving adhesion between the carbon nano-tubes and the resin and reducing agglomeration between various ones of the carbon nano-tubes. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electro-mechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than about 10 microns. Other apparatuses and methods are disclosed.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Myung Jin Yim, Jason M. Brand
  • Patent number: 10923341
    Abstract: A method of forming an oxide layer, the method including forming a first material layer on a semiconductor substrate, the first material layer including a polysiloxane material, wherein, from among Si—H1, Si—H2, and Si—H3 bonds included in the polysiloxane material, a percentage of Si—H2 bonds ranges from about 40% to about 90%, performing a first annealing process on the first material layer in an inert atmosphere, and performing a second annealing process on the first material layer in an oxidative atmosphere.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 16, 2021
    Assignees: Samsung Electronics Co., Ltd., Adeka Corporation
    Inventors: Jin-wook Park, Tae-jin Yim, Youn-joung Cho, Hiroshi Morita, Yasuhisa Furihata
  • Patent number: 10748632
    Abstract: A nonvolatile memory device includes multiple memory cells including first memory cells and second memory cells. A method of programming the nonvolatile memory device includes: performing first programming to apply a programming forcing voltage to a bit line of each of the first memory cells; and dividing the second memory cells into a first cell group, a second cell group, and a third cell group, based on a threshold voltage of the second memory cells after performing the first programming. The method also includes performing second programming to apply a programming inhibition voltage to the bit line of each of the first memory cells and a bit line of each of memory cells of the first cell group. A level of the programming forcing voltage is lower than that of the programming inhibition voltage.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Won Yun, Hye-Jin Yim
  • Patent number: 10727368
    Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Myung Jin Yim, Seungjae Lee, Sandeep Razdan
  • Patent number: 10714194
    Abstract: A method is provided for operating a memory device. The method includes counting, from among memory cells, a number of first off-cells with respect to a first reading voltage and a number of second off-cells with respect to a second reading voltage, comparing the number of first off-cells and the number of second off-cells, and determining, based on a result of the comparing, whether a programming error exists in a storage region in which the memory cells are included.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Jin Yim, Sang-Yong Yoon
  • Publication number: 20200200987
    Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.
    Type: Application
    Filed: September 28, 2017
    Publication date: June 25, 2020
    Inventors: Sang Yup Kim, Myung Jin Yim, Woosung Kim
  • Patent number: 10535804
    Abstract: A light-emitting device package of an embodiment includes a light-emitting structure including first and second conductive semiconductor layers and an active layer disposed between the first and second conductive semiconductor layers; a light-transmitting electrode layer disposed on the second conductive semiconductor layer; a passivation layer disposed on the second conductive semiconductor layer and a mesa-exposed portion of the first conductive semiconductor layer; a reflection layer disposed from the top of the light-transmitting electrode layer to the top of the passivation layer in a horizontal direction perpendicular to the thickness direction of the light-emitting structure; and a conductive capping layer disposed on the reflection layer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: January 14, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Bum Jin Yim
  • Publication number: 20190364748
    Abstract: Disclosed are a method and apparatus for expressing a seeding line for artificial enhancement of rain in airborne experiments considering cloud water. The method includes calculating average cloud liquid water path (LWP) for each time zone in a target region based on numerical weather prediction (NWP) model data for the target region, calculating an average wind direction and wind velocity in the target region, calculating a middle point and left and right end points of a seeding line candidate which is based on the average wind direction and wind velocity, calculating a seeding line by correcting the seeding line candidate based on a point at which cloud liquid water contents (LWC) is a maximum within upper, lower, left and right selection regions around the middle point and a height at the point, and expressing the seeding line and the height of the seeding line as an optimal seeding line and seeding height if the maximum value of the LWC is greater than 0.
    Type: Application
    Filed: November 21, 2018
    Publication date: December 5, 2019
    Inventors: Sanghee Chae, Ki-Ho Chang, Kyung-Eak Kim, Jin-Yim Jeong, Baek-Jo Kim, Joowan Cha, Woonseon Jung
  • Publication number: 20190324223
    Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a mold material, wherein a plurality of die are embedded in the mold material, a package substrate, wherein the mold material comprising the plurality of die is at least partially embedded in a cavity of the substrate, and wherein a liner is between side and bottom portions of the mold material and the package substrate, at least one optical die disposed on the package substrate, and a thermal solution disposed on a top surface of the optical die.
    Type: Application
    Filed: December 29, 2016
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Myung Jin Yim, Sang Yup Kim
  • Publication number: 20190302379
    Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.
    Type: Application
    Filed: July 14, 2016
    Publication date: October 3, 2019
    Inventors: Vivek RAGHUNATHAN, Myung Jin YIM
  • Publication number: 20190279862
    Abstract: A method of forming an oxide layer, the method including forming a first material layer on a semiconductor substrate, the first material layer including a polysiloxane material, wherein, from among Si—H1, Si—H2, and Si—H3 bonds included in the polysiloxane material, a percentage of Si—H2 bonds ranges from about 40% to about 90%, performing a first annealing process on the first material layer in an inert atmosphere, and performing a second annealing process on the first material layer in an oxidative atmosphere.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 12, 2019
    Applicant: ADEKA CORPORATION
    Inventors: Jin-wook PARK, Tae-jin YIM, Youn-joung CHO, Hiroshi MORITA, Yasuhisa FURIHATA
  • Patent number: 10381519
    Abstract: A light emitting device package, according to an embodiment, includes: a substrate; a light emitting structure that is disposed below the substrate and includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a first bonding pad connected with the first conductive type semiconductor layer while being embedded in a through-hole exposed the first conductive type semiconductor layer by passing through the active layer and the second conductive type semiconductor layer; a second bonding pad that is disposed below the second conductive type semiconductor layer while being spaced apart from the first bonding pad and is connected with the second conductive type semiconductor layer; a first insulation layer disposed on the lateral portion of the light emitting structure in the through-hole and on the lower inner edge of the light emitting structure; and a second insulation layer disposed between the first insulation layer and the first bonding pad in the
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: August 13, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jae Won Seo, Hoe Jun Kim, Bum Jin Yim, Jun Hee Hong
  • Patent number: D887669
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 23, 2020
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Eun Sun Park, Seung Eun Park, Na Ri Shin, Hye Jin Yim, Ki Hwang Park
  • Patent number: D889767
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 14, 2020
    Assignee: CJ CheilJedang Corporation
    Inventors: Eun Sun Park, Seung Eun Park, Na Ri Shin, Hye Jin Yim, Ki Hwang Park
  • Patent number: D890469
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 21, 2020
    Assignee: CJ CheilJedang Corporation
    Inventors: Eun Sun Park, Seung Eun Park, Na Ri Shin, Hye Jin Yim, Ki Hwang Park
  • Patent number: D890470
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 21, 2020
    Assignee: CJ CheilJedang Corporation
    Inventors: Eun Sun Park, Seung Eun Park, Na Ri Shin, Hye Jin Yim, Ki Hwang Park
  • Patent number: D891028
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 28, 2020
    Assignee: CJ CheilJedang Corporation
    Inventors: Eun Sun Park, Seung Eun Park, Na Ri Shin, Hye Jin Yim, Ki Hwang Park
  • Patent number: D891029
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 28, 2020
    Assignee: CJ CheilJedang Corporation
    Inventors: Eun Sun Park, Seung Eun Park, Na Ri Shin, Hye Jin Yim, Ki Hwang Park
  • Patent number: D891030
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 28, 2020
    Assignee: CJ CheilJedang Corporation
    Inventors: Eun Sun Park, Seung Eun Park, Na Ri Shin, Hye Jin Yim, Ki Hwang Park
  • Patent number: D891727
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: August 4, 2020
    Assignee: CJ CheilJedang Corporation
    Inventors: Eun Sun Park, Seung Eun Park, Na Ri Shin, Hye Jin Yim, Ki Hwang Park