Abstract: A flash memory includes memory cell array having memory cells divided into sectors, a page buffer block having groups of page buffers corresponding to the sectors, and a page buffer controller configured to control the groups of page buffers individually. In some embodiments, multiple groups of page buffers may be activated simultaneously to access multiple sectors, while page buffer groups for unselected sectors are deactivated.

Abstract: Disclosed is a page buffer for a nonvolatile semiconductor memory device and a related method of operation. The page buffer includes a unidirectional driver between a loading latch unit used for storing a data bit in the page buffer and a bitline used to program a memory cell connected to the page buffer.

Abstract: A flash memory device may include a pump, a regulator to control the pump so that an output voltage of the pump is substantially maintained at a target voltage, and a control circuit to control the regulator so that the pump selectively generates a program voltage or an erase voltage. In some embodiments, the output voltage of the pump may be stepped in response to program loop iterations during a program operation, or set to a target voltage during an erase operation.

Abstract: In one aspect, a word line enable method in a flash memory device includes driving a signal line corresponding to a selected word line with a word line voltage, and stepwise increasing a gate voltage of a switch transistor connected between the selected word line and the signal line during a program execute period.

Abstract: A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

Abstract: A flash memory device includes a memory cell array having a first region and a second region that include memory cells arranged in a plurality of rows and columns; an address storage circuit adapted to store address information for defining the second region; a row decoder circuit adapted to select one of the first and second regions in response to an external address; a voltage generating circuit adapted to generate a read voltage to be provided to a row of the selected region by the row decoder circuit during a read operation; a detecting circuit adapted to detect whether the selected region is included in the second region on the basis of address information and external address information that are stored in the address storage circuit; and a control logic adapted to control the voltage generating circuit in response to an output of the detecting circuit during the read operation.

Abstract: A non-volatile semiconductor memory device and/or a data processing system include a non-volatile memory array having a plurality of memory blocks and a write-protection control circuit that controls access to blocks of memory based on a start block address and an end block address. The write-protection control circuit may store start and end block addresses of an unlock region of the non-volatile memory array, and selectively activate a write enable signal according to the relationship between a write address and the start and end block addresses.

Abstract: A power-voltage driver circuit includes a first MOS transistor configured to turn a second MOS transistor off when a high-voltage generator provides a high voltage output. Related methods are also disclosed.

Abstract: The disclosure is NAND flash memory device with a partial copy-back mode, comprised of a cell array constructed of pages, a page buffer block composed of page buffers storing data in correspondence with the pages, a selection circuit for designating one or more pages to be initialized in the partial copy-back mode, and a control circuit for generating control signals to operate the page buffers and the selection circuit.

Abstract: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal.

Abstract: A non-volatile memory device comprises a memory cell array having a plurality of non-volatile memory cells arranged in rows and columns. Selected memory cells are programmed by applying program voltages thereto. Next, data bits stored in the selected cells are read. Then, a first column scan operation is performed to determine whether any of the selected memory cells is inadequately programmed. Upon determining that at least one of the selected memory cells is inadequately programmed, a second column scan operation is performed to detect a total number of the selected memory cells that are inadequately programmed. Upon determining that the total number of the selected memory cells that are inadequately programmed is less than a number that can be corrected by an error correcting circuit, the program operation terminates with a program pass status.

Abstract: A method of programming a flash memory device includes charging selection lines with a first voltage while applying program data to bit lines to during a bit line setup interval, then activating a block word line to electrically connect the selection lines to corresponding word lines, and then applying a second voltage, greater than the first voltage, to a selected one of the selection lines.

Abstract: A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

Abstract: Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.

Abstract: Provided is a method for discharging an erase voltage of a semiconductor memory device and discharge circuit for performing the method, the method including performing a first discharge on a common source line (CSL) of the semiconductor memory device, comparing the detected CSL voltage with a predetermined reference voltage, and performing a second discharge on the CSL when the detected CSL voltage is lower than a predetermined reference voltage.

Abstract: A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.

Abstract: In an embodiment, a method of driving a program operation in a nonvolatile semiconductor memory device is operable without discharging a bitline connected to a memory cell to be programmed between a program period and a verifying period. This remarkably improves programming speed and reduces current consumption.

Abstract: A non-volatile memory device includes page buffers arranged in groups, each group being coupled to a corresponding data output line so that data from more than one of the page buffers in each group may be simultaneously represented on the corresponding data output line during a program verification operation. Page buffers may be arranged in repair units with data from more than one page buffer simultaneously coupled to a data output line during a column scan operation.

Abstract: A fuse-free circuit may include a NAND flash memory cell, and a switch to turn on or off in response to data stored in the NAND flash memory cell. The fuse-free circuit may be embodied in a semiconductor device that also includes an adjustable circuit coupled to the switch. The adjustable circuit may be structured to emulate the No_Cut or Cut operation of a fuse in response to the on or off state of the switch.

Abstract: A flash memory device includes a memory cell array and an address decoding circuit configured to select bitlines and wordlines of the memory cell array. The device further includes a data sensing circuit configured to read data from a cell of the memory cell array responsive to a selected bitline and wordline and to output the read data without waiting for recovery of the selected bitline and wordline. The data sensing circuit may be configured to output the read data concurrent with recovery of the selected bitline and wordline.