Abstract: Disclosed is semiconductor memory device and a method for correcting a data error therein. The device comprises a memory cell array that stores a plurality of data bits and a plurality of check bits corresponding to the plurality of data bits. A read circuit is further provided that performs an operation of reading out the plurality of data bits and the plurality of check bits from the memory cell array. The semiconductor memory device further comprises error circuits for correcting a first error in the data bits of the first group and a second error in the data bits of the second group, respectively. The error circuit receives in parallel odd-numbered and even-numbered data and check bits read out from the memory cell array during a first cycle of a read mode of operation and generates first syndrome bits and second syndrome bits.

Abstract: Disclosed herein is a nonvolatile semiconductor memory device which comprises a memory cell array, page buffers and Y-pass gate circuit. Each page buffer according to the present invention contains its latch which has a first current driving capacity during a sensing period of a read operation and a second current driving capacity during a data output period of the read operation. Similar adjustable current drive capacity is provided during a program operation of the memory device. Preferably, such additional current drive capacity is provided via dual parallel pull-up transistors provided within a data latch circuit corresponding with each bit line of the memory device. Provision of the second parallel transistor and associated gating eliminates the need for one of the prior art circuit inverters in the latch, thereby reducing layout space over-all within the page buffer circuit region of the device.