Patents by Inventor Jing-Cheng Lin

Jing-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit structure and method for reducing polymer layer delamination
    Patent number: 11081475
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Underfill structure for semiconductor packages and methods of forming the same
    Patent number: 11075133
    Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
  • InFO-POP structures with TIVs having cavities
    Patent number: 11075168
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Semiconductor package and manufacturing method thereof
    Patent number: 11069673
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Methods and structures for packaging semiconductor dies
    Patent number: 11069653
    Abstract: A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface; forming a molding compound layer over the dies, wherein the top surface of the dies are covered by the molding compound layer; removing a first portion of the molding compound layer; removing a second portion of the molding compound layer such that the top surface of the dies is not covered by the molding compound layer; forming a redistribution layer (RDL) over the top surface of the dies; forming a plurality of solder balls over at least a portion of the RDL; and singulating the dies.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Jing-Cheng Lin
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20210217736
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Inventors: JING-CHENG LIN, YING-CHING SHIH, PU WANG, CHEN-HUA YU
  • Semiconductor device
    Patent number: 11062987
    Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai
  • Package Structure and Method
    Publication number: 20210210399
    Abstract: In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 8, 2021
    Inventors: Jing-Cheng Lin, Szu-Wei Lu, Chen-Hua Yu
  • SEMICONDUCTOR ASSEMBLIES INCLUDING COMBINATION MEMORY AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20210210500
    Abstract: Semiconductor devices including vertically-stacked combination memory devices and associated systems and methods are disclosed herein. The vertically-stacked combination memory devices include at least one volatile memory die and at least one non-volatile memory die stacked on top of each other. The corresponding stack may be attached to a controller die that is configured to provide interface for the attached volatile and non-volatile memory dies.
    Type: Application
    Filed: December 16, 2020
    Publication date: July 8, 2021
    Inventor: Jing Cheng Lin
  • Underfill Structure for Semiconductor Packages and Methods of Forming the Same
    Publication number: 20210210400
    Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 8, 2021
    Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
  • Integrated fan-out structure with rugged interconnect
    Patent number: 11056436
    Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
  • Semiconductor device and method of manufacture
    Patent number: 11056471
    Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen
  • Thermal dissipation through seal rings in 3DIC structure
    Patent number: 11037854
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Interconnect structure for package-on-package devices
    Patent number: 11037861
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • 3DIC Architecture with Interposer or Bonding Dies
    Publication number: 20210167018
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 3, 2021
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • SEMICONDUCTOR PACKAGES
    Publication number: 20210159147
    Abstract: A semiconductor package includes a semiconductor die, a first thermal conductive pattern and a second thermal conductive pattern. The semiconductor die is encapsulated by an encapsulant. The first thermal conductive pattern is disposed aside the semiconductor die in the encapsulant. The second thermal conductive pattern is disposed over the semiconductor die, wherein the first thermal conductive pattern is thermally coupled to the semiconductor die through the second thermal conductive pattern and electrically insulated from the semiconductor die.
    Type: Application
    Filed: February 5, 2021
    Publication date: May 27, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu
  • Semiconductor device including solder bracing material with a rough surface, and manufacturing method thereof
    Patent number: 11018106
    Abstract: A semiconductor device includes a first substrate including a plurality of first pads disposed on a first surface of the first substrate, a second substrate including a plurality of second pads disposed on a second surface of the substrate, a plurality of conductive bumps bonded the plurality of first pads with the plurality of second pads correspondingly, a solder bracing material disposed on the first surface and surrounded the plurality of conductive bumps, an underfill material surrounded the plurality of conductive bumps and disposed between the solder bracing material and the second surface, and a rough interface between the solder bracing material and the underfill material. The rough interface includes a plurality of protruded portions and a plurality of recessed portions.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jing-Cheng Lin, Feng-Cheng Hsu
  • Sawing Underfill in Packaging Processes
    Publication number: 20210125964
    Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo, Jing-Cheng Lin
  • Through-Substrate Vias with Improved Connections
    Publication number: 20210125900
    Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
    Type: Application
    Filed: January 5, 2021
    Publication date: April 29, 2021
    Inventors: Jing-Cheng Lin, Ku-Feng Yang
  • Methods of packaging semiconductor devices including placing semiconductor devices into die caves
    Patent number: 10964594
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung