Patents by Inventor Jing-Cheng Lin

Jing-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220122868
    Abstract: The present disclosure is an alignment mechanism of a bonding machine, in particular an alignment mechanism of a wafer bonding machine, which mainly has a support pedestal, at least three first alignment pins, and at least three second alignment pins, a first cam and a second cam. When the first cam rotates relative to the support pedestal, it will drive the first alignment pin to move relative to the support pedestal to position the first substrate on the support pedestal. When the second cam rotates relative to the support pedestal, it drives the second alignment pin to move relative to the support pedestal to position the second substrate above the first substrate, so that the second substrate is aligned with the first substrate to facilitate bonding the first substrate and the second substrate.
    Type: Application
    Filed: March 11, 2021
    Publication date: April 21, 2022
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, Mao-chan Chang
  • Publication number: 20220119945
    Abstract: An atomic layer deposition equipment capable of reducing precursor deposition and an atomic layer deposition process method using the same are disclosed. The atomic layer deposition equipment includes a chamber, a stage, a precursor inlet, a shielding component, at least one gas inlet, and at least one pumping port, wherein the stage and the shielding component are disposed in a containing space of the chamber. The shielding component shields part of the inner surface of the chamber, and the gas inlet is fluidly connected to the containing space for introducing an inactive gas to the space between the chamber and the shielding component to prevent the precursor from entering. The pumping port pumps out the precursors that have not reacted with a substrate, thereby reducing the precursors remaining on the inner surface of the chamber, prolonging the cleaning cycle of the chamber and improving the product yield.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: JING-CHENG LIN, TA-HAO KUO
  • Publication number: 20220119946
    Abstract: An atomic layer deposition equipment and an atomic layer deposition process method are disclosed. The atomic layer deposition equipment includes a chamber, a substrate stage, at least one bottom pumping port, at least one hollow component, a baffle and a shower head assembly, wherein the hollow component has an exhaust hole. The baffle is below the hollow component and forms an upper exhaust path with the hollow component, so that the flow field of the precursor in the atomic layer deposition process can be adjusted to a slow flow field to make a uniform deposition on the substrate.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: JING-CHENG LIN, CHING-LIANG YI, YUN-CHI HSU, HSIN-YU YAO
  • Publication number: 20220106686
    Abstract: A detachable atomic layer deposition apparatus for powders is disclosed, which includes a vacuum chamber, a shaft sealing device, and a driving unit. The driving unit is connected to the shaft sealing device. The vacuum chamber is fixed to one end of the shaft sealing device via at least one fixing member. The driving unit drives the vacuum chamber to rotate via the shaft sealing device to agitate the powders in a reaction space of the vacuum chamber to facilitate the formation of thin films with uniform thickness on the surface of the powders. In addition, the vacuum chamber can be removed from the shaft sealing device for users to take out the powders from the vacuum chamber and clean the vacuum chamber, thereby improving the convenience in usage.
    Type: Application
    Filed: May 30, 2021
    Publication date: April 7, 2022
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, CHIA-CHENG KU
  • Publication number: 20220106684
    Abstract: An atomic layer deposition apparatus for coating on fine powders is disclosed, which includes a vacuum chamber, a shaft sealing device, and a driving unit. The shaft sealing device includes an outer tube and an inner tube arranged in an accommodating space of the outer tube. The driving unit drives the vacuum chamber to rotate through the outer tube to agitate the fine powders in a reaction space of the vacuum chamber. An air extraction line and an air intake line are arranged in a connection space of the inner tube. The air extraction line is used to extract gas from the reaction space. The air intake line is used to transport non-reactive gas to the reaction space to blow the fine powders around in the reaction space and precursor gas to the reaction space to form thin films with uniform thickness on the surface of the fine powders.
    Type: Application
    Filed: March 11, 2021
    Publication date: April 7, 2022
    Inventors: JING-CHENG LIN, CHING-LIANG YI, JUNG-HUA CHANG, CHIA-CHENG KU
  • Publication number: 20220106685
    Abstract: An atomic layer deposition apparatus for coating particles is disclosed. The atomic layer deposition apparatus includes a vacuum chamber, a shaft sealing device, and a driving unit. The driving unit is connected to and drives the vacuum chamber to rotate through the shaft sealing device. The vacuum chamber includes a reaction space for accommodating a plurality of particles, wherein the reaction space has a polygonal columnar shape or a wavy circular columnar shape. An air extraction line and an air intake line are fluidly connected to the vacuum chamber, and the air intake line is used to transport a precursor gas and a non-reactive gas to the reaction space. Through the special shape of the reaction space together with the non-reactive gas, the particles in the reaction space can be effectively stirred to form a thin film with a uniform thickness on the surface of each particle.
    Type: Application
    Filed: March 11, 2021
    Publication date: April 7, 2022
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, TA-HAO KUO, CHIA-CHENG KU
  • Publication number: 20220106682
    Abstract: An atomic layer deposition apparatus for powders is disclosed. The atomic layer deposition apparatus includes a vacuum chamber, a shaft sealing device, and a driving unit. The shaft sealing device includes an outer tube and an inner tube, wherein the inner tube extends from an accommodating space of the outer tube to a reaction space of the vacuum chamber, forming a protruding tube part in the reaction space. The driving unit drives the vacuum chamber to rotate through the outer tube to agitate the powders in the reaction space. The ratio between the protruding tube part and the reaction space is within a specific range, so that a non-reactive gas delivered to the reaction space blows the powders around in the reaction space and spreads the powders to various areas of the reaction space to form a thin film with a uniform thickness on the surface of the powders.
    Type: Application
    Filed: May 30, 2021
    Publication date: April 7, 2022
    Inventors: JING-CHENG LIN, JUNG-HUA CHANG, CHIA-CHENG KU
  • Patent number: 11296011
    Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ku-Feng Yang
  • Patent number: 11282793
    Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 11270976
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsulant. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Publication number: 20220068612
    Abstract: The present disclosure provides an equipment for thin-film deposition or pre-cleaning which includes a chamber, a support pedestal, a fixing ring and a plurality of fixing members, wherein the support pedestal, the fixing ring and the fixing members are positioned within the chamber. The support pedestal has a supporting surface that supports a wafer, the fixing ring is connected to the support pedestal and surrounds the support pedestal and the wafer. When the fixing ring is disposed on the support pedestal, the fixing members contact the wafer, to fix the wafer on the support pedestal. The supporting surface of the support pedestal is at a height level same as or lower than the upper surface of the fixing ring is, to prevent the fixing ring from blocking an edge area of the wafer, to facilitate forming an evenly-distributed and steady plasma.
    Type: Application
    Filed: March 11, 2021
    Publication date: March 3, 2022
    Inventors: JING-CHENG LIN, Yao-Syuan Cheng
  • Patent number: 11264363
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure, a redistribution line, and a seal ring structure. The redistribution line and the seal ring structure are in the dielectric structure, the seal ring structure continuously surrounds the redistribution line, the seal ring structure includes a first seal ring and a second seal ring over and electrically connected to the first seal ring, and the redistribution structure has a first sidewall, a first surface, and a second surface opposite to the first surface. The chip package structure includes a chip structure over the first surface. The chip package structure includes a ground bump over the second surface. The chip package structure includes a conductive shielding film covering the chip structure and the first sidewall of the redistribution structure.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin, Po-Hao Tsai
  • Publication number: 20220059515
    Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 24, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng LIN, Po-Hao TSAI
  • Patent number: 11257715
    Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
  • Patent number: 11251071
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Patent number: 11239138
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 11205579
    Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: December 21, 2021
    Assignee: Taiwan Seminconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chin-Chuan Chang, Jui-Pin Hung, Szu-Wei Lu, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 11205615
    Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Jing-Cheng Lin, Pu Wang, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11201135
    Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the semiconductor package has a plurality of through substrate vias (TSVs) extending through an interposer substrate. A redistribution structure is arranged over a first surface of the interposer substrate, and a first die is bonded to the redistribution structure. An edge of the first die is beyond a nearest edge of the interposer substrate. A second die is bonded to the redistribution structure. The second die is laterally separated from the first die by a space.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Shang-Yun Hou
  • Patent number: 11183473
    Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface. The first die is attached to the first surface of the substrate by first electrical connectors. The second die is attached to the first surface of the substrate by second electrical connectors. A size of one of the second electrical connectors is smaller than a size of one of the first electrical connectors.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Chen-Hua Yu, Jing-Cheng Lin