Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

Abstract: The present disclosure is a substrate-processing chamber with a shielding mechanism with the same, which includes a reaction chamber, a substrate carrier, a storage chamber and a shielding mechanism. The reaction chamber is connected to the storage chamber, the substrate carrier is within the reaction chamber. The shielding mechanism includes at least one driving shaft, at least one connecting seat and a shield, wherein the driving shaft extends from the storage chamber to the reaction chamber. The connecting seat is connected to the shield and the driving shaft, wherein the driving shaft drives the shield to move between the storage chamber and the reaction chamber, via the connecting seat.

Abstract: An atomic layer deposition device is disclosed. The atomic layer deposition device includes a chamber, a precursor inlet, a heater, a support unit, a hollow component, and a baffle. When the heater and the support unit are driven by a lifting device to approach the hollow component, the support unit and the baffle surround and set bounds to a reaction space, so that the flow field of the process fluid, such as precursor or purge gas, can be adjusted stably to make a uniform deposition on the substrate.

Abstract: A shower head assembly of an atomic layer deposition device has a first trapezoidal column component, a second trapezoidal column component and a column component, wherein a first bottom edge of the first trapezoidal column component is connected to a second top edge of the second trapezoidal column component, and a second bottom edge of the second trapezoidal column component is connected to a top edge of the column component. The first trapezoidal column component has a first bottom dimension distance, the second trapezoidal column component has a second vertical distance, and the column component has a column vertical distance, wherein a ratio of the column vertical distance to the second vertical distance is greater than or equal to 1.2, and a total distance of the second vertical distance and the column vertical distance is less than the first bottom dimension distance.

Abstract: The present disclosure provides a laser lift-off method for separating substrate and semiconductor-epitaxial structure, which includes: providing at least one semiconductor device, wherein the semiconductor device includes a substrate and at least one semiconductor-epitaxial structure disposed in a stack-up manner; irradiating a laser onto an edge area of the semiconductor device to separate portions of the substrate and the semiconductor-epitaxial structure in the edge area; and pressing against the edge area of the semiconductor device vis a pressing device, then irradiating the laser onto an inner area of the semiconductor device to separate portions of the substrate and the semiconductor-epitaxial structure in the inner area wherein gas is generated during separating the portions of the substrate and the semiconductor-epitaxial structure in the inner area and evacuated from the edge area, to prevent damage of the semiconductor-epitaxial structure during the separating process.

Abstract: A method is provided that includes operations as follows: bonding an epitaxial layer formed with a first semiconductor substrate and an ion-implanted layer that is formed between the epitaxial layer and the first semiconductor substrate, to a bonding oxide layer of a second semiconductor substrate; separating the first semiconductor substrate from the epitaxial layer, by removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping the epitaxial layer; and forming a first semiconductor device portion on the epitaxial layer, and an interconnect layer on the first semiconductor device portion.

Abstract: An atomic layer deposition equipment capable of reducing precursor deposition and an atomic layer deposition process method using the same are disclosed. The atomic layer deposition equipment includes a chamber, a stage, a precursor inlet, a shielding component, at least one gas inlet, and at least one pumping port, wherein the stage and the shielding component are disposed in a containing space of the chamber. The shielding component shields part of the inner surface of the chamber, and the gas inlet is fluidly connected to the containing space for introducing an inactive gas to the space between the chamber and the shielding component to prevent the precursor from entering. The pumping port pumps out the precursors that have not reacted with a substrate, thereby reducing the precursors remaining on the inner surface of the chamber, prolonging the cleaning cycle of the chamber and improving the product yield.

Abstract: The present disclosure provides a wafer-holding device and a deposition equipment using the same, wherein the wafer-holding device includes a carrier, a first-lid ring and a second-lid ring. The carrier has a carrying surface for carrying a wafer thereon, and includes a first aligner disposed to enclose the carrying surface. The second-lid ring is connected to the first-lid ring, and includes a second aligner. The first-lid ring has a circumference larger than that of the second-lid ring, for carrying the second-lid ring thereon. The carrier is movable, and when the carrier carries the wafer thereon toward the lid rings, the first aligner thereon contacts, engages with the second aligner of the second-lid ring, thereby the second aligner is positioned to contact a specific area of the wafer and hold the wafer on the carrier, for the deposition equipment to perform a thin-film-deposition process to the wafer.

Abstract: The present disclosure provides a wafer-holding device, which mainly includes a wafer carrier, a first lid ring and a second lid ring, wherein the wafer carrier includes a carrying surface for carrying a wafer. The second lid ring is connected to the first-lid ring and placed on a radial-inner side of the first lid ring, wherein the first lid ring has a circumference larger than that of the second lid ring, for carrying the second lid ring. When the wafer carrier moves toward the first lid ring and the second lid ring, the second lid ring contacts the wafer on the wafer carrier, to fasten the wafer on the carrying surface of the wafer carrier, for performing a thin-film deposition to the wafer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

Abstract: An atomic layer deposition equipment and an atomic layer deposition process method are disclosed. The atomic layer deposition equipment includes a chamber, a substrate stage, at least one bottom pumping port, at least one hollow component, a baffle and a shower head assembly, wherein the hollow component has an exhaust hole. The baffle is below the hollow component and forms an upper exhaust path with the hollow component, so that the flow field of the precursor in the atomic layer deposition process can be adjusted to a slow flow field to make a uniform deposition on the substrate.

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Abstract: The present disclosure is a wafer support, which includes a heating unit, an insulating-and-heat-conducting unit and a conduct portion, wherein the insulating-and-heat-conducting unit is positioned between the conduct portion and the heating unit. During a deposition process, an AC bias is formed on the conduct portion to attract a plasma disposed thereabove. The heating unit includes at least one heating coil, wherein the heating coil heats the wafer supported by the wafer support via the insulating-and-heat-conducting unit and the conduct portion. The insulating-and-heat-conducting unit electrically insulates the heating unit and the conduct portion to prevent the AC flowing in the heating coil and the AC bias on the conduct portion from conducting each other, so the wafer support can generate a stable AC bias and temperature to facilitate forming an evenly-distributed thin film on the wafer supported by the wafer support.

Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.