Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.

Abstract: A topical pharmaceutical composition containing diacerein and/or its analogs is provided. Also provided is a method for treating various diseases using this topical pharmaceutical composition.

Abstract: An environmental sensitive electronic device package including a first substrate, a second substrate, an environmental sensitive electronic device, a side wall barrier structure, a first adhesive, and a second adhesive is provided. The environmental sensitive electronic device is located on the first substrate. The first adhesive is located on the first substrate. The side wall barrier structure is located on the first adhesive, and the side wall barrier structure is adhered to the first substrate through the first adhesive. The second adhesive is located on the side wall barrier structure. The side wall barrier structure is adhered to the second substrate through the second adhesive, and the side wall barrier structure, the first adhesive, and the second adhesive are located between the first substrate and the second substrate. A manufacturing method of an environmental sensitive electronic device package is also provided.

Abstract: A catalyst for a catalytic ink includes a support particle and a metallic material supported on the support particle. The metallic material is diamminesilver hydroxide, a silver salt, a palladium salt, a gold salt, chloroauric acid, or combinations thereof. A catalytic ink obtained from the catalyst and use of the same to fabricate a conductive circuit are also disclosed.

Abstract: This invention concerns in general treatment of diseases and pathological conditions with anti-VEGF antibodies. More specifically, the invention concerns the treatment of human patients susceptible to or diagnosed with cancer using an anti-VEGF antibody, preferably in combination with one or more additional anti-tumor therapeutic agents for the treatment of ovarian cancer.

Abstract: A measurement method, a measurement apparatus, and a computer program product for measuring a thermoelectric module are provided. A temperature is provided to the thermoelectric module. A current is applied to the thermoelectric module to turn both sides of the thermoelectric module into a hot side and a cold side. The temperature of the hot side is higher than that of the cold side. A terminal voltage of the thermoelectric module, a hot side temperature of the hot side, and a cold side temperature of the cold side are measured at different time points. A thermoelectric relationship between the terminal voltages and differences between the hot side temperatures and the corresponding cold side temperatures is obtained according to the terminal voltages, the hot side temperatures, and the cold side temperatures. At least one first parameter of the thermoelectric module is estimated according to the thermoelectric relationship.

Abstract: An electronic device including at least one electronic component and a method of manufacturing the same are provided. The electronic device may include a substrate, a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer, and a first metal layer disposed on the insulating layer. The insulating layer may have a pattern corresponding to a pattern of the semiconductor layer or the first metal layer. The flexible layer has a Young's modulus less than 40 GPa and is disposed on the substrate to encapsulate the semiconductor layer. At least one first opening penetrates the flexible layer. At least one second metal layer is disposed on the flexible layer and in the first opening and electrically connected to the semiconductor layer.

Abstract: An electronic component and a method for fabricating the electronic component are provided. The electronic component includes a carrier, a first metal layer, a dielectric layer, a semiconductor layer, a flexible layer, at least one first opening, and at least one second metal layer. The first metal layer is disposed on the carrier. The dielectric layer is disposed on the first metal layer, and has a pattern consistent with a pattern of the dielectric layer. The semiconductor layer is disposed on the dielectric layer. The flexible layer is disposed on the carrier and encapsulates the first metal layer, the dielectric layer and the semiconductor layer. The flexible layer has a Young's modulus less than 40 GPa. The first opening penetrates the flexible layer. The second metal layer is disposed on the flexible layer and in the first opening and is electrically connected with the semiconductor layer.

Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.

Abstract: A method of forming a patterned metal unit on an article. The method includes the steps of: providing an article that has an insulating surface; transferring a catalyst layer onto the insulating surface of the article, the catalyst layer including a catalytic material; removing a part of the catalyst layer to form a patterned catalyst layer; and forming a patterned metal layer on the patterned catalyst layer by an electroless plating technique to obtain a patterned metal unit that is constituted by the patterned catalyst layer and the patterned metal layer.

Abstract: An electronic device including at least one electronic component and a method of manufacturing the same are provided. The electronic device may include a substrate, a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer, and a first metal layer disposed on the insulating layer. The insulating layer may have a pattern corresponding to a pattern of the semiconductor layer or the first metal layer. The flexible layer has a Young's modulus less than 40 GPa and is disposed on the substrate to encapsulate the semiconductor layer. At least one first opening penetrates the flexible layer. At least one second metal layer is disposed on the flexible layer and in the first opening and electrically connected to the semiconductor layer.

Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure may include a substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The semiconductor layer is adjacent to the first dielectric layer or the second dielectric layer. The semiconductor layer is disposed on the first dielectric layer or the second dielectric layer. The first conductive layer is adjacent to the first dielectric layer or the second dielectric layer. The second conductive layer is disposed on the first dielectric layer or the second dielectric layer. The effective Young's modulus of the second dielectric layer may be smaller than the Young's modulus of the first dielectric layer.

Abstract: This invention provides Chelating Complex Micelles as a drug carrier. The Chelating Complex Micelles can load drugs without changing their structure, and therefore extend the half-life of drugs in the human body. The chelating complex micelles contain a metal ion core, at least one polymer, and at least one drug molecule. The metal ion is considered as a Lewis acid while polymer chain and drug molecules are referred to as Lewis bases. The drug molecule is linked to the polymer via forming coordinate bonds with metal ion, and then self-assembled to form chelating complex micelles as a drug carrier.

Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.

Abstract: This invention provides Chelating Complex Micelles as a drug carrier. The Chelating Complex Micelles can load drugs without changing their structure, and therefore extend the half-life of drugs in the human body. The chelating complex micelles contain a metal ion core, at least one polymer, and at least one drug molecule. The metal ion is considered as a Lewis acid while polymer chain and drug molecules are referred to as Lewis bases. The drug molecule is linked to the polymer via forming coordinate bonds with metal ion, and then self-assembled to form chelating complex micelles as a drug carrier.

Abstract: This invention provides Chelating Complex Micelles as a drug carrier. The Chelating Complex Micelles can load drugs without changing their structure, and therefore extend the half-life of drugs in the human body. The chelating complex micelles contain a metal ion core, at least one polymer, and at least one drug molecule. The metal ion is considered as a Lewis acid while polymer chain and drug molecules are referred to as Lewis bases. The drug molecule is linked to the polymer via forming coordinate bonds with metal ion, and then self-assembled to form chelating complex micelles as a drug carrier.

Abstract: An electronic component and a method for fabricating the electronic component are provided. The electronic component includes a carrier, a first metal layer, a dielectric layer, a semiconductor layer, a flexible layer, at least one first opening, and at least one second metal layer. The first metal layer is disposed on the carrier. The dielectric layer is disposed on the first metal layer, and has a pattern consistent with a pattern of the dielectric layer. The semiconductor layer is disposed on the dielectric layer. The flexible layer is disposed on the carrier and encapsulates the first metal layer, the dielectric layer and the semiconductor layer. The flexible layer has a Young's modulus less than 40 GPa. The first opening penetrates the flexible layer. The second metal layer is disposed on the flexible layer and in the first opening and is electrically connected with the semiconductor layer.

Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.