Patents by Inventor Jingwei Bai

Jingwei Bai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9117652
    Abstract: A method for forming porous metal structures and the resulting structure may include forming a metal structure above a substrate. A masking layer may be formed above the metal structure, and then etched using a reactive ion etching process with a mask etchant and a metal etchant. Etching the masking layer may result in the formation of a plurality of pores in the metal structure. In some embodiments, the metal structure may include a first end region, a second end region, and an intermediate region. Before etching the masking layer, a protective layer may be formed above the first end region and the second end region, so that the plurality of pores is contained within the intermediate region. In some embodiments, the intermediate metal region may be a nanostructure such as a nanowire.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yann Astier, Jingwei Bai, Robert L. Bruce, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 9097698
    Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 4, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yann A. N. Astier, Jingwei Bai, Satyavolu S. Papa Rao, Kathleen B. Reuter, Joshua T. Smith
  • Patent number: 9085120
    Abstract: Solid state nanopore devices for nanopore applications and methods of manufacture are disclosed herein. The method includes forming a membrane layer on an underlying substrate. The method further includes forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further includes forming a membrane over the sacrificial material. The method further includes removing the sacrificial material within the hole and portions of the underlying substrate. The method further includes drilling an opening in the membrane, aligned with the hole.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 21, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann Astier, Jingwei Bai, Satyavolu Papa Rao, Kathleen Reuter, Joshua T. Smith
  • Patent number: 9059135
    Abstract: Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes.
    Type: Grant
    Filed: August 18, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jingwei Bai, Evan G. Colgan, Christopher V. Jahnes, Stanislav Polonsky
  • Publication number: 20150153320
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.
    Type: Application
    Filed: January 28, 2015
    Publication date: June 4, 2015
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20150144887
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 28, 2015
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20150144888
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 28, 2015
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20150137069
    Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Inventors: Yann A.N. Astier, Jingwei Bai, Satyavolu S. Papa Rao, Kathleen B. Reuter, Joshua T. Smith
  • Publication number: 20150140716
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Patent number: 9012882
    Abstract: A graphene nanomesh includes a sheet of graphene having a plurality of periodically arranged apertures, wherein the plurality of apertures have a substantially uniform periodicity and substantially uniform neck width. The graphene nanomesh can open up a large band gap in a sheet of graphene to create a semiconducting thin film. The periodicity and neck width of the apertures formed in the graphene nanomesh may be tuned to alter the electrical properties of the graphene nanomesh. The graphene nanomesh is prepared with block copolymer lithography. Graphene nanomesh field-effect transistors (FETs) can support currents nearly 100 times greater than individual graphene nanoribbon devices and the on-off ratio, which is comparable with values achieved in nanoribbon devices, can be tuned by varying the neck width. The graphene nanomesh may also be incorporated into FET-type sensor devices.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: April 21, 2015
    Assignee: The Regents of the University of California
    Inventors: Xiangfeng Duan, Yu Huang, Jingwei Bai
  • Patent number: 9012329
    Abstract: A nanogap of controlled width in-between noble metals is produced using sidewall techniques and chemical-mechanical-polishing. Electrical connections are provided to enable current measurements across the nanogap for analytical purposes. The nanogap in-between noble metals may also be formed inside a Damascene trench. The nanogap in-between noble metals may also be inserted into a crossed slit nanopore framework. A noble metal layer on the side of the nanogap may have sub-layers serving the purpose of multiple simultaneous electrical measurements.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yann Astier, Jingwei Bai, Michael F. Lofaro, Satyavolu S. Papa Rao, Joshua T. Smith, Chao Wang
  • Publication number: 20150056407
    Abstract: Solid state nanopore devices for nanopore applications and methods of manufacture are disclosed herein. The method includes forming a membrane layer on an underlying substrate. The method further includes forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further includes forming a membrane over the sacrificial material. The method further includes removing the sacrificial material within the hole and portions of the underlying substrate. The method further includes drilling an opening in the membrane, aligned with the hole.
    Type: Application
    Filed: September 11, 2013
    Publication date: February 26, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann ASTIER, Jingwei BAI, Satyavolu PAPA RAO, Kathleen REUTER, Joshua T. SMITH
  • Publication number: 20150056732
    Abstract: Solid state nanopore devices for nanopore applications and methods of manufacture are disclosed herein. The method includes forming a membrane layer on an underlying substrate. The method further includes forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further includes forming a membrane over the sacrificial material. The method further includes removing the sacrificial material within the hole and portions of the underlying substrate. The method further includes drilling an opening in the membrane, aligned with the hole.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann ASTIER, Jingwei BAI, Satyavolu PAPA RAO, Kathleen REUTER, Joshua T. SMITH
  • Publication number: 20150001079
    Abstract: A nanodevice includes a nanochannel disposed through a dielectric material. A first electrode is disposed on a first side of the nanochannel, is formed within the dielectric material and has a surface exposed within the nanochannel. A second electrode is disposed on a second side of the nanochannel, is formed within the dielectric material and has a surface exposed within the nanochannel opposite the first electrode. A power circuit is connected between the first and second electrodes to create a potential difference between the first and second electrodes such that portions of a molecule can be identified by a change in electrical properties across the first and second electrodes as the molecule passes.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: JINGWEI BAI, Niina S. Haiminen, Laximi P. Parida, Gustavo A. Stolovitzky
  • Publication number: 20150001099
    Abstract: A nanodevice includes a nanochannel disposed through a dielectric material. A first electrode is disposed on a first side of the nanochannel, is formed within the dielectric material and has a surface exposed within the nanochannel. A second electrode is disposed on a second side of the nanochannel, is formed within the dielectric material and has a surface exposed within the nanochannel opposite the first electrode. A power circuit is connected between the first and second electrodes to create a potential difference between the first and second electrodes such that portions of a molecule can be identified by a change in electrical properties across the first and second electrodes as the molecule passes.
    Type: Application
    Filed: August 15, 2013
    Publication date: January 1, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingwei Bai, Niina S. Haiminen, Laxmi P. Parida, Gustavo A. Stolovitzky
  • Publication number: 20140374695
    Abstract: An anti-retraction capping material is formed on a surface of a nanowire that is located upon a dielectric membrane. A gap is then formed into the anti-retraction capping material and nanowire forming first and second capped nanowire structures of a nanodevice. The nanodevice can be used for recognition tunneling measurements including, for example DNA sequencing. The anti-retraction capping material serves as a mobility barrier to pin, i.e., confine, a nanowire portion of each of the first and second capped nanowire structures in place, allowing long-term structural stability. In some embodiments, interelectrode leakage through solution during recognition tunneling measurements can be minimized.
    Type: Application
    Filed: September 30, 2013
    Publication date: December 25, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann A. N. Astier, Jingwei Bai, Satyavolu S. Papa Rao, Kathleen B. Reuter, Joshua T. Smith
  • Publication number: 20140377900
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap.
    Type: Application
    Filed: July 18, 2013
    Publication date: December 25, 2014
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20140374694
    Abstract: A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Yann Astier, Jingwei Bai, Michael A. Guillorn, Satyavolu S. Papa Rao, Joshua T. Smith
  • Publication number: 20140367749
    Abstract: Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Inventors: Jingwei Bai, Evan G. Colgan, Christopher V. Jahnes, Stanislav Polonsky
  • Publication number: 20140370637
    Abstract: Nanochannel sensors and methods for constructing nanochannel sensors. An example method includes forming a sacrificial line on an insulating layer, forming a dielectric layer, etching a pair of electrode trenches, forming a pair of electrodes, and removing the sacrificial line to form a nanochannel. The dielectric layer may be formed on insulating layer and around the sacrificial line. The pair of electrode trenches may be etched in the dielectric layer on opposite sides of the sacrificial line. The pair of electrodes may be formed by filling the electrode trenches with electrode material. The sacrificial line may be removed by forming a nanochannel between the at least one pair of electrodes.
    Type: Application
    Filed: August 18, 2013
    Publication date: December 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Jingwei Bai, Evan G. Colgan, Christopher V. Jahnes, Stanislav Polonsky