Abstract: The embodiments of the present disclosure recognize the potential benefits of semiconductor IC device fabrication techniques to form a microdevice, such as a transistor, that includes structures, such as a source and/or drain, that are to be connected to a backside contact that is further associated with a backside back end of line (BEOL) network. The semiconductor IC device includes a bottom isolation extension (BIE) region. The BIE region is formed within a gate structure of the microdevice and may be located between the backside contact and the gate structure. The BIE region may provide for increased electrical isolation between the backside contact and the gate structure.

Abstract: A semiconductor structure provides a spacer directly contacting a sidewall of portion of a hardmask material, a sidewall of a portion of a backside interlayer dielectric material, and a sidewall of a portion of a semiconductor substrate on the portion of a hardmask material. The spacer resides directly below and contacts a liner of a shallow trench isolation that is between a passive device region and an active device region. The spacer prevents undercutting of the semiconductor substrate in the protected region between the active device region and the passive device region during backside contact formation.

Abstract: A calibrator bottle and method of calibration. The calibrator bottle includes a plastic material that is doped or compounded with a fluorescent material system that fluoresces in a target range and may be used to calibrate a blood culture instrument that measures sample fluorescence to determine bottle positivity or negativity. Also described herein is a system and method to control the temperature of samples in a blood culture apparatus using a resistance temperature device (RTD) device that measures the temperature of the sample. The sample measurements are correlated with the ambient temperature to determine an ambient temperature that will provide a target bottle content temperature.

Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

Abstract: A transistor includes one or more tapered inner spacers. The tapered inner spacer may include a base region that extends or protrudes beyond a plane that is coplanar with a first sidewall of the gate. The base region(s) may reduce the gate length of the gate adjacent to the base region. When two base regions are associated with the same gate, the two base regions may merge and may be between and/or isolate the gate from the underlying substrate. The tapered inner spacers may result in reduced parasitic capacitances between gate and the substrate and/or between the gate and adjacent source/drain region(s), and/or may reduce current leakage from the gate into the substrate or other underlying structure.

Abstract: Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.

Abstract: An in-situ chip design is provided for self-heating free characterization of a device under test (DUT) with a short time constant. The in-situ chip design includes a pulse generator configured to output a pulse to the DUT and a buffering circuit arranged between the pulse generator and the DUT. The buffering circuit includes a first switch and an adjustable buffer circuit in parallel with the first switch and being controllable to apply one of various degrees of buffering to the pulse.

Abstract: A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.

Abstract: A semiconductor structure is provided that includes a tunable and shared non-conductive layer as part of a gate stack of at least a pair of nanosheet GAA transistors with a shared metal gate electrode. The semiconductor structure has a tunable non-conductive material/gate dielectric area ratio where the non-conductive material is not constrained to a periphery of the nanosheet stack cross section.

Abstract: A semiconductor structure, a system, and a method of forming a multi-silicide structure for stacked FETs within the semiconductor. The semiconductor structure may include an NFET. The semiconductor structure may also include a PFET. The semiconductor structure may also include an NFET silicide proximately connected to the NFET, where the NFET silicide is a first material. The semiconductor structure may also include a PFET silicide proximately connected to the PFET, where the PFET silicide is a second material different than the first material. The system may include the semiconductor structure. The method may include forming an NFET silicide proximately connected to an NFET, where the NFET silicide is a first material. The method may also include forming a PFET silicide proximately connected to a PFET, where the PFET silicide is a second material different than the first material.

Abstract: A transistor includes a gate structure with reduced gate region or eliminated gate region located between a top MDI region and a bottom MDI region. The reduced gate region has a reduction of conductive material therewithin and may be formed due to the presence of prefabricated wide inner spacers between the top MDI region and the bottom MDI region. The no gate region has an absence of conductive material therewithin and may be formed due to the presence of a prefabricated inner spacer that is between, and has a coplanar perimeter with, the top MDI region and the bottom MDI region. By reducing or eliminating the conductive material of the gate structure between the dual MDI structure, parasitic capacitance otherwise associated therewith is reduced.

Abstract: A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

Abstract: A method is applied to an electronic device. The electronic device includes a basic application layer, a basic service layer, and an access layer, the access layer includes a first access layer and a second access layer, and the first access layer and the second access layer support different data transmission capabilities. The method includes: The basic application layer requests the basic service layer to establish a service channel for a communication service of an application. The basic service layer establishes a transmission channel group for the communication service if the communication service supports multilink transmission. The transmission channel group includes a first service channel and/or a second service channel, the first service channel corresponds to the first access layer, and the second service channel corresponds to the second access layer. The electronic device transmits service data of the communication service based on the transmission channel group.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first distance and having a first critical voltage. A second MTJ having a second distance and having a second critical voltage, wherein the first distance and the second distance are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.

Abstract: In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Abstract: A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

Abstract: A Bluetooth communication method is disclosed, and relates to the field of short-range wireless communications technologies. The method includes: A terminal receives a play operation performed by a user on first audio data. The terminal sends first indication information to a Bluetooth device when a service type of the first audio data is a first service type, where the first indication information is used by the Bluetooth device to set a buffer time length for the audio data to first duration. The Bluetooth device receives the first audio data sent by the terminal via Bluetooth, and buffers the first audio data. The Bluetooth device starts to play the buffered first audio data when the buffer time length for the first audio data reaches the first duration. In this way, the terminal can perform targeted delay control on audio data playback of the Bluetooth device in different application scenarios.