Abstract: A transistor includes a gate structure with reduced gate region or eliminated gate region located between a top MDI region and a bottom MDI region. The reduced gate region has a reduction of conductive material therewithin and may be formed due to the presence of prefabricated wide inner spacers between the top MDI region and the bottom MDI region. The no gate region has an absence of conductive material therewithin and may be formed due to the presence of a prefabricated inner spacer that is between, and has a coplanar perimeter with, the top MDI region and the bottom MDI region. By reducing or eliminating the conductive material of the gate structure between the dual MDI structure, parasitic capacitance otherwise associated therewith is reduced.

Abstract: A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.

Abstract: A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

Abstract: A method is applied to an electronic device. The electronic device includes a basic application layer, a basic service layer, and an access layer, the access layer includes a first access layer and a second access layer, and the first access layer and the second access layer support different data transmission capabilities. The method includes: The basic application layer requests the basic service layer to establish a service channel for a communication service of an application. The basic service layer establishes a transmission channel group for the communication service if the communication service supports multilink transmission. The transmission channel group includes a first service channel and/or a second service channel, the first service channel corresponds to the first access layer, and the second service channel corresponds to the second access layer. The electronic device transmits service data of the communication service based on the transmission channel group.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first distance and having a first critical voltage. A second MTJ having a second distance and having a second critical voltage, wherein the first distance and the second distance are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.

Abstract: In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Abstract: A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

Abstract: A Bluetooth communication method is disclosed, and relates to the field of short-range wireless communications technologies. The method includes: A terminal receives a play operation performed by a user on first audio data. The terminal sends first indication information to a Bluetooth device when a service type of the first audio data is a first service type, where the first indication information is used by the Bluetooth device to set a buffer time length for the audio data to first duration. The Bluetooth device receives the first audio data sent by the terminal via Bluetooth, and buffers the first audio data. The Bluetooth device starts to play the buffered first audio data when the buffer time length for the first audio data reaches the first duration. In this way, the terminal can perform targeted delay control on audio data playback of the Bluetooth device in different application scenarios.

Abstract: A method includes: A basic application layer sends first information that includes a first business requirement and a first port to a basic service layer. The basic service layer sends second information that includes the first business requirement, a first broadcast business channel, and a logical channel type to an access layer. The first broadcast business channel is determined based on the first information. The access layer supports a first access technology that is determined, based on the first business requirement, from a plurality of access technologies supported by the access layer. The access layer sends a first mapping relationship that indicates the first broadcast business channel and a first logical channel to the basic service layer. The first logical channel is a logical channel that supports the first access technology and that is determined based on the second information.

Abstract: A semiconductor structure includes a nanosheet channel stack disposed on a semiconductor substrate. The nanosheet channel stack includes one or more layers of a semiconducting material providing nanosheet channels for one or more nanosheet field-effect transistors and an insulator layer as the bottom most layer disposed on the semiconductor substrate. The semiconductor structure further includes an epitaxial oxide spacer layer disposed on outer ends of a bottom surface of the insulator layer and extending downwardly into the substrate; shallow trench isolation regions disposed adjacent the nanosheet channel stack and extending downwardly from a top surface of the semiconductor substrate, wherein a portion of each of the shallow trench isolation regions is disposed on an outer sidewall of the respective epitaxial oxide spacer layer; and a gate surrounding the nanosheet channel stack and on a top surface of each of the shallow trench isolation regions.

Abstract: A method of fabrication a semiconductor device includes forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further includes forming an isolation wall in the isolation region, where the isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further includes forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall, and forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: An imaging module to obtain an image of an entire bottle in one image frame. The imaging module places the bottle in an auxiliary mirror module (AMM). The module has a quasi-conical shaped mirror which offers a reflection of the bottle placed in the AMM. That reflection is the source of an image obtained by an imaging assembly. The imaging assembly can be a lens/camera assembly or a photo sensor that will detect photo fluorescence.

Abstract: A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Abstract: Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. A portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.

Abstract: Stacked FET devices having wrap-around contacts to optimize contact resistance and techniques for formation thereof are provided. In one aspect, a stacked FET device includes: a bottom-level FET(s) on a substrate; lower contact vias present in an ILD disposed over the bottom-level FET(s); a top-level FET(s) present over the lower contact vias; and top-level FET source/drain contacts that wrap-around source/drain regions of the top-level FET(s), wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the bottom-level FET(s). When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top-level FET source/drain contacts. A method of forming a stacked FET device is also provided.

Abstract: A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.