Patents by Inventor Jingyun Zhang

Jingyun Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230054540
    Abstract: Stacked FET devices having wrap-around contacts to optimize contact resistance and techniques for formation thereof are provided. In one aspect, a stacked FET device includes: a bottom-level FET(s) on a substrate; lower contact vias present in an ILD disposed over the bottom-level FET(s); a top-level FET(s) present over the lower contact vias; and top-level FET source/drain contacts that wrap-around source/drain regions of the top-level FET(s), wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the bottom-level FET(s). When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top-level FET source/drain contacts. A method of forming a stacked FET device is also provided.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 23, 2023
    Inventors: Ruilong Xie, Heng Wu, Jingyun Zhang, Julien Frougier
  • Patent number: 11587837
    Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 21, 2023
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang
  • Publication number: 20230041159
    Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.
    Type: Application
    Filed: August 9, 2021
    Publication date: February 9, 2023
    Inventors: Jingyun Zhang, REINALDO VEGA, MIAOMIAO WANG, Takashi Ando
  • Patent number: 11575023
    Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clint Jason Oteri, Alexander Reznicek, Bahman Hekmatshoartabari, Jingyun Zhang, Ruilong Xie
  • Publication number: 20230026989
    Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
    Type: Application
    Filed: July 6, 2021
    Publication date: January 26, 2023
    Inventors: Jing Guo, Ekmini Anuja De Silva, Indira Seshadri, Jingyun Zhang, Su Chen Fan
  • Publication number: 20220416056
    Abstract: Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Jingyun Zhang, Ruilong Xie, REINALDO VEGA, Kangguo Cheng, Lan Yu
  • Patent number: 11527574
    Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: December 13, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek, Choonghyun Lee
  • Patent number: 11527616
    Abstract: A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-? metal gate disposed over the first set of fins, and a second high-? metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: December 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Alexander Reznicek
  • Publication number: 20220384574
    Abstract: A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Inventors: Julien Frougier, Sagarika Mukesh, RUQIANG BAO, Andrew M. Greene, Jingyun Zhang, Nicolas Loubet, Veeraraghavan S. Basker
  • Patent number: 11515392
    Abstract: An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: November 29, 2022
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, International Business Machines Corporation
    Inventors: Shay Reboh, Remi Coquand, Nicolas Loubet, Tenko Yamashita, Jingyun Zhang
  • Patent number: 11515214
    Abstract: Semiconductor devices and methods of forming the same include forming first recesses in a first stack of alternating sacrificial layers and channel layers. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers and the first inner spacer sub-layer are replaced with a gate stack in contact with the second inner spacer sub-layer.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: November 29, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Patent number: 11515217
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: November 29, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee, Pouya Hashemi, Jingyun Zhang
  • Publication number: 20220368754
    Abstract: A Bluetooth communication method is disclosed, and relates to the field of short-range wireless communications technologies. The method includes: A terminal receives a play operation performed by a user on first audio data. The terminal sends first indication information to a Bluetooth device when a service type of the first audio data is a first service type, where the first indication information is used by the Bluetooth device to set a buffer time length for the audio data to first duration. The Bluetooth device receives the first audio data sent by the terminal via Bluetooth, and buffers the first audio data. The Bluetooth device starts to play the buffered first audio data when the buffer time length for the first audio data reaches the first duration. In this way, the terminal can perform targeted delay control on audio data playback of the Bluetooth device in different application scenarios.
    Type: Application
    Filed: September 4, 2020
    Publication date: November 17, 2022
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yuhong ZHU, Jiongjin SU, Jingyun ZHANG, Guanjun NI
  • Patent number: 11502169
    Abstract: A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of first type sacrificial layers and active semiconductor layers. The method includes forming the first type sacrificial layer on sidewalls of the nanosheet stacks, then forming a dielectric pillar between the sidewall portions of the first type sacrificial layers of adjacent nanosheet stacks, and then removing the first type sacrificial layer. The method also includes forming a PWFM layer in spaces formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks, and includes forming a NWFM layer in spaces formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Jingyun Zhang, Xin Miao, Alexander Reznicek
  • Patent number: 11500614
    Abstract: An embodiment of the invention may include a method of forming and a resulting multiply-and-accumulate device. The device may include a capacitor in a second region. The capacitor comprises a dielectric located between a first metal contact and a second metal contact. The device may include a stacked nanosheet device in the first region from the nanosheet. The stacked nanosheet device may include a top transistor and a bottom transistor in contact with the first metal contact. The device may include a nanosheet device in the third region, wherein a source/drain of a transistor of the nanosheet device is in contact with the first metal contact.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: November 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ruilong Xie, Alexander Reznicek, Jingyun Zhang
  • Patent number: 11495668
    Abstract: Semiconductor devices and method of forming the same include recessing sacrificial layers relative to the channel layers, in a stack of vertically aligned, alternating sacrificial layers and channel layers, to form first recesses. A dual-layer dielectric is deposited that includes a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the first recesses. The first dielectric material is recessed relative to the second dielectric material to form second recesses. Additional second dielectric material is deposited to fill the second recesses. The second dielectric material and the additional second dielectric material is etched away to create air gaps.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang
  • Patent number: 11495669
    Abstract: Semiconductor devices include a stack of vertically arranged channel layers. A gate stack is formed above, between, and around the vertically arranged channel layers. Source and drain regions and source and drain conductive contacts are formed. Inner spacers are formed between the vertically arranged channel layers, each having an inner air gap and a recessed layer formed from a first dielectric material. Outer spacers are formed between the gate stack and the source and drain conductive contacts, each having a second dielectric material that is pinched off to form an outer air gap.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang
  • Publication number: 20220310602
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; a transistor stack structure formed on the semiconductor substrate, the transistor stack structure including a first FET and a second FET, where the first FET is a different polarity than the second FET; a first source-drain epitaxial layer of the first FET formed directly on the substrate adjacent to the first FET; and a second source-drain epitaxial layer of the second FET formed on the substrate adjacent to the second FET, wherein a bottom dielectric isolation layer is formed between the substrate and the second epitaxial layer.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Andrew M. Greene, Julien Frougier, Jingyun Zhang, Sung Dae Suk, Veeraraghavan S. Basker, Ruilong Xie
  • Patent number: 11450659
    Abstract: A semiconductor device including a decoupling capacitor disposed between adjacent device source-drain regions, the decoupling capacitor comprising an outer metal liner, a dielectric disposed adjacent to the outer metal liner, and an inner metal liner disposed adjacent to the dielectric, a single diffusion break isolation region disposed between the adjacent device source-drain regions. The outer metal liner is disposed in electrical contact with the adjacent device source-drain regions.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: September 20, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Ruilong Xie, Jingyun Zhang, Lan Yu
  • Patent number: 11444165
    Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. A gate stack is formed on the semiconductor fin, between the outer spacers.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 13, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi