Abstract: A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Abstract: A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.

Abstract: Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.

Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

Abstract: A semiconductor structure includes a semiconductor substrate, with first, second, and third field effect transistors (FETs) formed on the substrate. A gate of the first FET includes a gate electrode, a first work function metal (WFM) layered with a first interfacial layer (IL) and a first high-k dielectric (HK); a gate of the second FET includes the first WFM layered with a second IL, a second HK, and a first dipole material; and a gate of the third FET includes the first WFM layered with a third IL, a third HK, the first dipole material, and a second dipole material. The first FET does not include the first dipole material and does not include the second dipole material, and the second FET does not include the second dipole material.

Abstract: A point-to-multipoint data transmission method and device, the method including a left earbud and a right earbud of a true wireless stereo (TWS) headset separately performing pairing and service content negotiation with an electronic device. The left earbud receives left configuration information sent by the electronic device, to configure a left ISO channel, and the right earbud receives right configuration information sent by the electronic device, to configure a right ISO channel. The left earbud receives, based on the BLE-based audio profile, audio data that is sent by the electronic device through the left ISO channel, and the right earbud receives, based on the BLE-based audio profile, the audio data that is sent by the electronic device through the right ISO channel. The left earbud and the right earbud play the respectively received audio data based on a first timestamp.

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.

Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack on a substrate. The nanosheet stack includes an alternating sequence of sacrificial nanosheets and channel nanosheets. The sacrificial nanosheets include second nanosheets located between first nanosheets and third nanosheets. The first nanosheets and the third nanosheets have a first germanium concentration that is lower than a second germanium concentration of the second nanosheets. The sacrificial nanosheets are selectively etched and the lower first germanium concentration causes the first nanosheets and the third nanosheets to be etched slower than the second nanosheets creating an indentation region on opposing sides of the nanosheet stack. The indentation region has a narrowing shape towards remaining second nanosheets of the sacrificial nanosheets.

Abstract: A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.

Abstract: An audio data transmission method. An electronic device transmits audio data to a first earbud of a TWS headset by using a first CIS of a first CIG, and transmits audio data to a second earbud of the TWS headset by using a second CIS of the first CIG. The electronic device determines that the TWS headset is switched from a double-earbud mode (namely, a mode in which the first earbud and the second earbud are used together as audio input/output devices of the electronic device) to a first single-earbud mode (namely, a mode in which the first earbud is independently used as an audio input/output device of the electronic device). In response to the determining, the electronic device deactivates the second CIS, stops transmitting audio data to the second earbud by using the second CIS, and continues transmitting audio data to the first earbud by using the first CIS.

Abstract: A semiconductor device includes a substrate material with a semiconductor material with a predetermined crystal orientation, a gate stack having a plurality of nanosheet channel layers, each nanosheet channel layer being controlled by metal gate layers located above and below the nanosheet channel layer, each nanosheet channel layer having the same semiconductor material and crystal orientation as that of the substrate, and a source/drain region on opposite sides of the gate stack. Each source/drain region includes bridging structures respectively connected to each nanosheet channel layer.

Abstract: A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Embodiments of the invention are directed to a transistor that includes a source or drain (S/D) region having an S/D formation assistance region, wherein the S/D formation assistance region includes a top surface, sidewalls, and a bottom surface. The S/D formation assistance region is at least partially within a portion of a substrate. An S/D isolation region is formed around the sidewalls and the bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

Abstract: A semiconductor structure includes a semiconductor substrate, with first, second, and third field effect transistors (FETs) formed on the substrate. A gate of the first FET includes a gate electrode, a first work function metal (WFM) layered with a first interfacial layer (IL) and a first high-k dielectric (HK); a gate of the second FET includes the first WFM layered with a second IL, a second HK, and a first dipole material; and a gate of the third FET includes the first WFM layered with a third IL, a third HK, the first dipole material, and a second dipole material. The first FET does not include the first dipole material and does not include the second dipole material, and the second FET does not include the second dipole material.

Abstract: A semiconductor structure, and a method of making the same, includes an inner spacer located between channel nanosheets on a semiconductor substrate, a first portion of the inner spacer located on a first side of the semiconductor structure and a second portion of the inner spacer located on a second side opposing the first side, the first portion of the inner spacer on the first side including a protruding region extending outwards from a middle top surface of the first portion of the inner spacer, and a metal gate stack in direct contact with the inner spacer, the first portion of the inner spacer including the protruding region pinching off the metal gate stack for increasing a threshold voltage on the first side.

Abstract: A semiconductor device including a first nanosheet device located on a substrate. The first nanosheet device includes a first plurality of nanosheets and each of the first plurality of nanosheets are surround by a first dipole. The first dipole has a first concentration of a first dipole material. A second nanosheet device located on the substrate. The second nanosheet device includes a second plurality of nanosheets and each of the second plurality of nanosheets are surround by a second dipole. The second dipole has a second concentration of a second dipole material. The first concentration and the second concentration are different.

Abstract: A MOSFET includes a semiconductor substrate, which has a body and an upper layer. The upper layer is doped differently than the body. The body and the upper layer are of a same crystal structure and orientation. The MOSFET also includes a p-type FET on the upper layer of the substrate. The p-type FET includes p-doped source/drain structures that sandwich one or more channels and a p gate stack with a p-type work function metal. In one or more embodiments, the p-doped source/drain structures are of the same crystal structure and orientation as the upper layer of the substrate and directly contact the upper layer of the substrate. In one or more embodiments, the upper layer of the substrate is doped differently than the p-doped source/drain structures, such that the p-doped source/drain structures and the upper layer of the substrate form pn-type diodes.

Abstract: A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.