Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

Abstract: A method of forming a semiconductor device that includes providing a first stack of nanosheets having a first thickness and a second stack of nanosheets having a second thickness; and forming a oxide layer on the first and second stack of nanosheets. The oxide layer fills a space between said nanosheets in the first stack, and is conformally present on the nanosheets in the second stack. The method further includes forming a work function metal layer on the first and second stack of nanosheets. In some embodiments, the work function metal layer is present on only exterior surfaces of the first stack to provide a single gate structure and is conformally present about an entirety of the nanosheets in the second stack to provide a multiple gate structure.

Abstract: A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.

Abstract: A semiconductor structure includes a substrate, an isolation layer disposed over the substrate, a plurality of nanosheet channels, interfacial layers surrounding each of the nanosheet channels, and dielectric layers surrounding each of the interfacial layers. The plurality of nanosheet channels includes first and second sets of two or more nanosheet channels for first and second NFETs and third and fourth sets of two or more nanosheet channels for first and second PFETs. The interfacial layers surrounding the first and third sets of nanosheet channels for the first NFET and the first PFET have a first thickness, and interfacial layers surrounding the second and fourth sets of nanosheets channels for the second NFET and the second PFET have a second thickness smaller than the first thickness. The first NFET has a higher threshold voltage than the second NFET, and the first PFET has a lower threshold voltage than the second PFET.

Abstract: A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area.

Abstract: A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

Abstract: A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets.

Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.

Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.

Abstract: A semiconductor device includes a substrate material with a semiconductor material with a predetermined crystal orientation, a gate stack having a plurality of nanosheet channel layers, each nanosheet channel layer being controlled by metal gate layers located above and below the nanosheet channel layer, each nanosheet channel layer having the same semiconductor material and crystal orientation as that of the substrate, and a source/drain region on opposite sides of the gate stack. Each source/drain region includes bridging structures respectively connected to each nanosheet channel layer.

Abstract: Methods of forming a semiconductor device include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.

Abstract: A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET S/D structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.

Abstract: A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels, interfacial layers formed around the first channels, and dielectric material including first and second portions having respective thicknesses formed on the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels, the interfacial layers formed around the second channels, and the dielectric material formed on the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating channel layers and sacrificial layers. The sacrificial layers are recessed relative to the channel layers. Inner spacers are formed at ends of the sacrificial layers with a process that preferentially forms dielectric material on the sacrificial layers relative to the channel layers. Source and drain structures are formed at ends of the channel layers. The sacrificial layers are etched away to expose surfaces of the channel layers. A gate stack is formed on and around the channel layers.

Abstract: A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.

Abstract: A semiconductor device includes a first nanosheet stack, a second nanosheet stack, and a third nanosheet stack arranged on a substrate. The semiconductor device includes a gate arranged on the first nanosheet stack, the second nanosheet stack, and the third nanosheet stack. The semiconductor device includes a channel extending through the gate and from the first nanosheet stack, the second nanosheet stack, and to the third nanosheet stack in a serpentine fashion. The semiconductor device includes a first source/drain and a second source/drain arranged on opposing sides of the gate.

Abstract: A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET S/D structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.