Abstract: A system comprises a front opening universal pod (FOUP) configured to hold one or more semiconductor wafers and a load dock having a stage and a receiving portion extending above the stage. The FOUP is positioned on the stage. A fan filter unit (FFU) positioned above the load dock. An air flow optimizer device is disposed on the receiving portion and under the FFU. The air flow optimizer device has an inlet opening and an outlet opening and a channel extends between the inlet opening and the outlet opening.

Abstract: A load port is capable of monitoring various environmental parameters associated with a transport carrier to minimize and/or prevent exposure of the semiconductor substrates therein to increased humidity, increased oxygen, increased vibration, and/or one or more other elevated environmental conditions that might otherwise contaminate the semiconductor substrates, damage the semiconductor substrates, and/or cause processing defects. For example, the load port may monitor the environmental parameters as indicators of a potential blockage of a diffuser of the transport carrier, and a relief valve may be used to divert a gas away from the transport carrier based on a determination that a diffuser blockage has occurred. In this way, the gas may be diverted through the relief valve and away from the transport carrier to prevent increased humidity, contaminants, and/or vibration from contaminating and/or damaging the semiconductor substrates.

Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.

Abstract: A wafer lift pin system is capable of dynamically modulating or adjusting the flow of gas into and out of lift pins of the wafer lift pin system to achieve and maintain a consistent pressure in supply lines that supply the gas to the lift pins. This enables the wafer lift pin system to precisely control the speed, acceleration, and deceleration of the lift pins to achieve consistent and repeatable lift pin rise times and fall times. A controller and various sensors and valves may control the gas pressures in the wafer lift pin system based on various factors, such as historic rise times, historic fall times, and/or the condition of the lift pins. This enables smoother and more controlled automatic operation of the lift pins, which reduces and/or minimizes wafer shifting and wafer instability, which may reduce processing defects and maintain or improve processing yields.

Abstract: An under-floor charging station can be mounted under a floor such that a top plate of the under-floor charging station is substantially flush with a top surface of the floor without touching the ground. Openings in the top plate allow charging elements to extend when in use to charge a mobile robot, and to retract under the floor when not in use. The retractable charging elements prevent tripping hazards and allow the mobile robot to move freely throughout a clean room. Moreover, because the charging elements can be retracted in an unobtrusive position when the under-floor charging station is not in use, the under-floor charging station is permitted to be positioned in locations in the clean room that allow the mobile robot to continue working while charging and/or allow non-stop running of the mobile robot.

Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.

Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.

Abstract: In an embodiment, a system includes: a warehousing apparatus configured to interface with a semiconductor die processing tool configured to process a semiconductor die singulated from a wafer, wherein the semiconductor die processing tool comprise an in-port and an out-port, wherein the warehousing apparatus is configured to: move a first die vessel that contains the semiconductor die to the in-port from a first die vessel container, wherein the first die vessel container is configured to house the first die vessel; move the first die vessel from the in-port to a buffer region; and move a second die vessel from the buffer region to the out-port.

Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.

Abstract: A multiple transport carrier docking device may be capable of storing and/or staging a plurality of transport carriers in a chamber of the multiple transport carrier docking device, and may be capable of forming an air-tight seal around a transport carrier in the chamber. Semiconductor wafers in the transport carrier may be accessed by a wafer transport tool while the air-tight seal around the transport carrier prevents and/or reduces the likelihood that contaminants in the semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers.

Abstract: A transport carrier docking device may be capable of forming an air-tight seal around a transport carrier while a front portion of the transport carrier is inserted into a chamber of the transport carrier docking device. Semiconductor wafers in the transport carrier may be accessed by a transport tool while the air-tight seal exists around the transport carrier, which prevents and/or reduces the likelihood that contaminants in a semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers.

Abstract: An apparatus and an operating method for automated wafer carrier handling are provided. The operation method includes bring a base frame and an engaging mechanism of an automated wafer carrier handling apparatus into abutting contact with a top flange mounted on a wafer carrier to limit at least one degree of freedom of movement of the top flange, where the engaging mechanism is disposed on the base frame; transporting the wafer carrier to a destination location by the automated wafer carrier handling apparatus; and releasing the top flange mounted on the wafer carrier from the automated wafer carrier handling apparatus at the destination location.

Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.

Abstract: An apparatus for handling wafer carriers in a semiconductor fabrication facility (FAB) is disclosed. In one example, the apparatus includes: a table configured to receive a wafer carrier having a first door and operable to hold a plurality of wafers; an opening mechanism configured to open the first door of the wafer carrier; and a door storage space configured to store the first door. The apparatus may be either located on a floor of the FAB or physically coupled to a ceiling of the FAB.

Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.

Abstract: In an embodiment, a system includes: a warehousing apparatus configured to interface with a semiconductor die processing tool configured to process a semiconductor die singulated from a wafer, wherein the semiconductor die processing tool comprise an in-port and an out-port, wherein the warehousing apparatus is configured to: move a first die vessel that contains the semiconductor die to the in-port from a first die vessel container, wherein the first die vessel container is configured to house the first die vessel; move the first die vessel from the in-port to a buffer region; and move a second die vessel from the buffer region to the out-port.

Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.

Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.

Abstract: A wafer sorting and stoking system provides automated storage and retrieval of wafer frames carrying semiconductor wafers. A wafer frame cassette is received at a transfer port from a transfer system. A robot arm retrieves the wafer frames from the cassette and stores each wafer frame in a respective storage slot in one of a plurality of storage towers. The storage location of each wafer frame is recorded. Each wafer frame can be selectively retrieved and loaded into a wafer frame cassette by the robot arm for further processing.

Abstract: A multiple transport carrier docking device may be capable of storing and/or staging a plurality of transport carriers in a chamber of the multiple transport carrier docking device, and may be capable of forming an air-tight seal around a transport carrier in the chamber. Semiconductor wafers in the transport carrier may be accessed by a wafer transport tool while the air-tight seal around the transport carrier prevents and/or reduces the likelihood that contaminants in the semiconductor fabrication facility will reach the semiconductor wafers. The air-tight seal around the transport carrier may reduce defects of the semiconductor wafers that might otherwise be caused by the contaminants, may increase manufacturing yield and quality in the semiconductor fabrication facility, and/or may permit the continued reduction in device and/or feature sizes of integrated circuits and/or semiconductor devices that are to be formed on semiconductor wafers.