Patents by Inventor Jiun-Rong Pai

Jiun-Rong Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10872794
    Abstract: A system and method for inline detection of defects on a semiconductor wafer surface during a semiconductor device manufacturing process is disclosed herein. In one embodiment, a method includes: automatically transporting the wafer from a first processing station to an inspection station; scanning a wafer surface using a camera in the inspection station; generating at least one image of the wafer surface; analyzing the at least one image to detect defects on the wafer surface based on a set of predetermined criteria; if the wafer is determined to be defective, automatically transporting the wafer from the inspection station to a stocker; and if the wafer is determined to be not defective, automatically transporting the wafer to a second processing station for further processing in accordance with the semiconductor device manufacturing process.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ko Liao, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Ya Hsun Hsueh
  • Patent number: 10861723
    Abstract: The present disclosure relates to a method of automatically re-programming an EFEM to account for positional changes of the EFEM robot. In some embodiments, the method is performed by determining an initial position of an EFEM robot within an EFEM chamber. The EFEM robot at the initial position moves along a first plurality of steps defined relative to the initial position and that extend along a path between a first position and a second position. Positional parameters are determined, which describe a change between an initial position and a new position of the EFEM robot that is different than the initial position. A second plurality of steps are determined based upon the positional parameters. The EFEM robot at the new position moves along the second plurality of steps defined relative to the new position and that extend along the path between the first position and the second position.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 10854490
    Abstract: A wafer carrier handling apparatus includes a housing, a platform, a moving mechanism and a door storage device. The platform is configured to hold a wafer carrier. The moving mechanism is connected to the housing and configured to move the platform with respect to the housing. The door storage device is disposed above the housing. The door storage device has a first door storage zone. The first door storage zone is configured to allow a door of the wafer carrier to be held thereon.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Sheng Kuo, Chih-Hung Huang, Ming-Hsien Tsai, Yang-Ann Chu, Hsuan Lee, Jiun-Rong Pai
  • Patent number: 10852704
    Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
  • Patent number: 10839507
    Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
  • Patent number: 10822181
    Abstract: In certain embodiments, a system includes: a source lane configured to move a first die container between a load port and a source lane staging area; an inspection sensor configured to produce a sensor result based on a die on the first die container; a pass target lane configured to move a second die container between a pass target lane out port and a pass target lane staging area; a fail target lane configured to move a third die container between a fail target lane out port and a fail target lane staging area; and a conveyor configured to move the die from the first die container at the source lane staging area to either the second die container at the pass target lane staging area or the fail target lane staging area based on the sensor result.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Chih-Hung Huang, Yi-Fam Shiu, Chueng-Jen Wang, Hsuan Lee, Jiun-Rong Pai
  • Publication number: 20200343115
    Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Cheng-Kang HU, Shou-Wen KUO, Sheng-Hsiang CHUANG, Jiun-Rong PAI, Hsu-Shui LIU
  • Publication number: 20200251367
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip processing tool. The integrated chip processing tool includes a first transfer module and a second transfer module. The first transfer module has a first robotic arm disposed within a housing. The first transfer module is configured to receive a single and unitary first die tray configured to hold a plurality of integrated chip (IC) die and to concurrently transfer all of the plurality of IC die held by the single and unitary first die tray to a single and unitary die boat. The second transfer module has an additional robotic arm disposed within the housing and configured to concurrently transfer all of the plurality of IC die from the single and unitary die boat to a single and unitary second die tray.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Pin-Yi Hsin, Shou-Wen Kuo, Patrick Lin
  • Patent number: 10734206
    Abstract: Some embodiments relate to a system. The system includes a radio frequency (RF) generator configured to output a RF signal. A transmission line is coupled to the RF generator. A plasma chamber is coupled to RF generator via the transmission line, wherein the plasma chamber is configured to generate a plasma based on the RF signal. A micro-arc detecting element is configured to determine whether a micro-arc has occurred in the plasma chamber based on the RF signal.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Kuang Wu, Chih-Kuo Chang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Sing-Tsung Li
  • Publication number: 20200243393
    Abstract: Some embodiments relate to a processing tool for processing a singulated semiconductor die. The tool includes an evaluation unit, a drying unit, and a die wipe station. The evaluation unit is configured to subject the singulated semiconductor die to a liquid to detect flaws in the singulated semiconductor die. The drying unit is configured to dry the liquid from a frontside of the singulated semiconductor die. The die wipe station includes an absorptive drying structure configured to absorb the liquid from a backside of the singulated semiconductor die after the drying unit has dried the liquid from the frontside of the singulated semiconductor die.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Yang-Ann Chu
  • Publication number: 20200227283
    Abstract: An apparatus for handling wafer carriers in a semiconductor fabrication facility (FAB) is disclosed. In one example, the apparatus includes: a table configured to receive a wafer carrier having a first door and operable to hold a plurality of wafers; an opening mechanism configured to open the first door of the wafer carrier; and a door storage space configured to store the first door. The apparatus may be either located on a floor of the FAB or physically coupled to a ceiling of the FAB.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Tsung-Sheng KUO, Yang-Ann CHU, Alan YANG, Vic HUANG, Hsu-Shui LIU, Jiun-Rong PAI
  • Patent number: 10714364
    Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing having an opening on a wall of the housing; a load port outside the housing; a robot arm inside the housing; and a processor. The load port is coupled to the wall and configured to load a wafer carrier for inspection. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Kang Hu, Shou-Wen Kuo, Sheng-Hsiang Chuang, Jiun-Rong Pai, Hsu-Shui Liu
  • Patent number: 10665507
    Abstract: Some embodiments relate to a processing tool for processing a singulated semiconductor die. The tool includes an evaluation unit, a drying unit, and a die wipe station. The evaluation unit is configured to subject the singulated semiconductor die to a liquid to detect flaws in the singulated semiconductor die. The drying unit is configured to dry the liquid from a frontside of the singulated semiconductor die. The die wipe station includes an absorptive drying structure configured to absorb the liquid from a backside of the singulated semiconductor die after the drying unit has dried the liquid from the frontside of the singulated semiconductor die.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Yang-Ann Chu
  • Patent number: 10665489
    Abstract: The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die between a die tray and a die boat, and an associated method. The integrated chip processing tool has a die exchanger configured to receive a die tray comprising a plurality of IC die. The die exchanger is configured to automatically transfer the plurality of IC die between the die tray and a die boat. An IC die processing tool is configured to receive the die boat from the die exchanger and to perform a processing step on the plurality of IC die within the die boat. By operating the die exchanger to automatically transfer IC die between the die tray and the die boat, the transfer time can be reduced and contamination and/or damage risks related to a manual transfer of IC die can be mitigated.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Pin-Yi Hsin, Shou-Wen Kuo, Patrick Lin
  • Publication number: 20200156884
    Abstract: In certain embodiments, a system includes: a source lane configured to move a first die container between a load port and a source lane staging area; an inspection sensor configured to produce a sensor result based on a die on the first die container; a pass target lane configured to move a second die container between a pass target lane out port and a pass target lane staging area; a fail target lane configured to move a third die container between a fail target lane out port and a fail target lane staging area; and a conveyor configured to move the die from the first die container at the source lane staging area to either the second die container at the pass target lane staging area or the fail target lane staging area based on the sensor result.
    Type: Application
    Filed: October 10, 2019
    Publication date: May 21, 2020
    Inventors: Tsung-Sheng Kuo, Chih-Hung Huang, Yi-Fam Shiu, Chueng-Jen Wang, Hsuan Lee, Jiun-Rong Pai
  • Publication number: 20200161161
    Abstract: Apparatus and methods for handling semiconductor part carriers are disclosed. In one example, an apparatus for handling semiconductor part carriers is disclosed. The apparatus includes a mechanical arm and an imaging system coupled to the mechanical arm. The mechanical arm is configured for holding a semiconductor part carrier. The imaging system is configured for automatically locating a goal position on a surface onto which the semiconductor part carrier is to be placed.
    Type: Application
    Filed: October 10, 2019
    Publication date: May 21, 2020
    Inventors: Ren-Hau WU, Yan-Han CHEN, Cheng-Kang HU, Feng-Kuang WU, Hsu-Shui LIU, Jiun-Rong PAI
  • Publication number: 20200161160
    Abstract: In an embodiment, a system includes: a tool port of a semiconductor processing tool; a processing port with an internal processing port location and an external processing port location; a robot configured to move a die vessel between the internal processing port location and the tool port; and an actuator configured to move the die vessel between the internal processing port location and the external processing port location.
    Type: Application
    Filed: September 30, 2019
    Publication date: May 21, 2020
    Inventors: Tsung-Sheng KUO, Yi-Fam SHIU, Eason CHEN, Yang-Ann CHU, Jiun-Rong PAI
  • Publication number: 20200130874
    Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.
    Type: Application
    Filed: June 14, 2019
    Publication date: April 30, 2020
    Inventors: Tsung-Sheng KUO, Hsu-Shui LIU, Jiun-Rong PAI, Yang-Ann CHAU, Chih-Chun LIN, Shine CHEN
  • Publication number: 20200118857
    Abstract: An operating method of a wafer cassette handling apparatus includes at least the following steps. A stage that carries a wafer cassette is moved into a main body of a wafer cassette handling apparatus to open a cassette door of the wafer cassette. The stage that carries the wafer cassette is moved out of the main body after the cassette door is opened. A wafer is extracted from the wafer cassette and transferred to a processing system. Another operating method and a wafer cassette handling apparatus are also provided.
    Type: Application
    Filed: December 15, 2019
    Publication date: April 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Hsuan Lee, Hsu-Shui Liu, Jiun-Rong Pai, Chih-Hung Huang, Yang-Ann Chu
  • Patent number: 10622236
    Abstract: An apparatus for handling wafer carriers in a semiconductor fabrication facility (FAB) is disclosed. In one example, the apparatus includes: a table configured to receive a wafer carrier having a first door and operable to hold a plurality of wafers; an opening mechanism configured to open the first door of the wafer carrier; and a door storage space configured to store the first door. The apparatus may be either located on a floor of the FAB or physically coupled to a ceiling of the FAB.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Alan Yang, Vic Huang, Hsu-Shui Liu, Jiun-Rong Pai