Patents by Inventor Joachim Mahler

Joachim Mahler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403556
    Abstract: A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Peter Irsigler, Joachim Mahler, Guenther Ruhl, Hans-Joachim Schulze, Markus Zundel
  • Patent number: 10396007
    Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Soon Lock Goh, Swee Kah Lee, Joachim Mahler, Mei Chin Ng, Beng Keh See, Guan Choon Matthew Nelson Tee
  • Patent number: 10396015
    Abstract: A semiconductor device includes a carrier, a semiconductor die and a die attach material arranged between the carrier and the semiconductor die. A fillet height of the die attach material is less than about 95% of a height of the semiconductor die. A maximum extension of the die attach material over edges of a main surface of the semiconductor die facing the die attach material is less than about 200 micrometers.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Benjamin Reichert, Chen Wen Lee, Giovanni Ragasa Garbin, Peter Strobel
  • Patent number: 10297564
    Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg
  • Publication number: 20190109112
    Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.
    Type: Application
    Filed: October 5, 2017
    Publication date: April 11, 2019
    Inventors: Joachim Mahler, Georg Meyer-Berg
  • Publication number: 20190103378
    Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Inventors: Irmgard Escher-Poeppel, Khalil Hosseini, Johannes Lodermeyer, Joachim Mahler, Thorsten Meyer, Georg Meyer-Berg, Ivan Nikitin, Reinhard Pufall, Edmund Riedl, Klaus Schmidt, Manfred Schneegans, Patrick Schwarz
  • Patent number: 10177112
    Abstract: A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: January 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Edward Fuergut, Georg Meyer-Berg
  • Publication number: 20180338379
    Abstract: An electronic device includes a component, an electronic component, and a joining material arranged between a surface of the component and a surface of the electronic component. Spacer elements are embedded in the joining material. Interconnects are arranged between the spacer elements and the surface of the component, and between the spacer elements and the surface of the electronic component.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 22, 2018
    Inventors: Thomas Bemmerl, Joachim Mahler
  • Patent number: 10121690
    Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Edward Fuergut, Joachim Mahler
  • Publication number: 20180315744
    Abstract: A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.
    Type: Application
    Filed: April 27, 2018
    Publication date: November 1, 2018
    Inventors: Joachim Mahler, Guenther Kolmeder
  • Patent number: 10049962
    Abstract: A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Edward Fuergut, Joachim Mahler
  • Patent number: 10038105
    Abstract: A semiconductor device includes at least one highly doped region of an electrical device arrangement formed in a semiconductor substrate and a contact structure including an NTC (negative temperature coefficient of resistance) portion arranged adjacent to the at least one highly doped region at a front side surface of the semiconductor substrate. The NTC portion includes a negative temperature coefficient of resistance material.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies AG
    Inventors: Thomas Basler, Joachim Mahler, Hans-Joachim Schulze
  • Patent number: 10020245
    Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: July 10, 2018
    Assignee: Infineon Technologies AG
    Inventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Stefan Landau
  • Patent number: 9988262
    Abstract: A method for fabricating an electronic device is disclosed. In one example, the method comprises providing a semiconductor wafer, forming a plurality of cavities into the semiconductor wafer, filling a stabilization material into the cavities, fabricating a temporary panel by applying a cap sheet onto the semiconductor wafer, the cap sheet covering the cavities, singulating the temporary panel into a plurality of semiconductor devices, fabricating an embedded wafer by embedding the semiconductor devices in an encapsulant, removing the cap sheet of each one of the semiconductor devices, and singulating the embedded wafer into a plurality of electronic devices.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 5, 2018
    Assignee: Infineon Technologies AG
    Inventors: Dominic Maier, Joachim Mahler, Daniel Porwol, Alfred Sigl
  • Patent number: 9984897
    Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 29, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Manfred Mengel, Joachim Mahler, Khalil Hosseini, Franz-Peter Kalz
  • Patent number: 9986636
    Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer. The polymer includes at least one of a carbon layer structure and a carbon-like layer structure.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 29, 2018
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Ralf Otremba
  • Patent number: 9953952
    Abstract: A semiconductor device includes a carrier, a chip attached to the carrier, a sealant vapor deposited over the chip and the carrier, and encapsulation material deposited over the sealed chip and the sealed carrier.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Michael Juerss, Stefan Landau
  • Patent number: 9941181
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 10, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Heinrich Koerner, Michael Bauer, Reimund Engl, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Publication number: 20180086632
    Abstract: A method for fabricating an electronic device is disclosed. In one example, the method comprises providing a semiconductor wafer, forming a plurality of cavities into the semiconductor wafer, filling a stabilization material into the cavities, fabricating a temporary panel by applying a cap sheet onto the semiconductor wafer, the cap sheet covering the cavities, singulating the temporary panel into a plurality of semiconductor devices, fabricating an embedded wafer by embedding the semiconductor devices in an encapsulant, removing the cap sheet of each one of the semiconductor devices, and singulating the embedded wafer into a plurality of electronic devices.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 29, 2018
    Applicant: Infineon Technologies AG
    Inventors: Dominic Maier, Joachim Mahler, Daniel Porwol, Alfred Sigl
  • Publication number: 20180040530
    Abstract: A semiconductor device includes a carrier, a semiconductor die and a die attach material arranged between the carrier and the semiconductor die. A fillet height of the die attach material is less than about 95% of a height of the semiconductor die. A maximum extension of the die attach material over edges of a main surface of the semiconductor die facing the die attach material is less than about 200 micrometers.
    Type: Application
    Filed: July 31, 2017
    Publication date: February 8, 2018
    Inventors: Joachim Mahler, Benjamin Reichert, Chen Wen Lee, Giovanni Ragasa Garbin, Peter Strobel