Patents by Inventor Joachim Mahler

Joachim Mahler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013132
    Abstract: A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Joachim Mahler, Giovanni Ragasa Garbin, Chen Wen Lee, Benjamin Reichert, Peter Strobel
  • Publication number: 20200395334
    Abstract: Disclosed is a method that includes: providing semiconductor dies, each of the semiconductor dies having a thinner active region surrounded by a thicker inactive region so that each of the semiconductor dies has a first cavity vertically aligned with the thinner active region and laterally surrounded by the thicker inactive region; providing a metal carrier having connection parts secured to the metal carrier, each of the connection parts dimensioned to fit within the first cavity of one of the semiconductor dies; inserting each of the connection parts of the metal carrier into the respective first cavity of the corresponding semiconductor die; after the inserting, attaching the metal carrier to the semiconductor dies; and after the attaching, singulating the metal carrier so that each of the connection parts of the metal carrier remains attached to the corresponding semiconductor die.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Joachim Mahler, Michael Bauer, Christoph Liebl, Georg Meyer-Berg, Georg Reuther, Peter Strobel
  • Patent number: 10854547
    Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 1, 2020
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg, Guenter Tutsch
  • Patent number: 10832992
    Abstract: A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Giovanni Ragasa Garbin, Chen Wen Lee, Benjamin Reichert, Peter Strobel
  • Publication number: 20200352034
    Abstract: A method includes providing a joining material between a surface of a component and a surface of an electronic component. A plurality of spacer elements is embedded in the joining material. The spacer elements are coated with a coating material. The coating material includes sinter particles. A dimension of the sinter particles is greater than 1 nanometer and smaller than 1000 nanometers. The method further includes forming interconnects from the coating material. The interconnects are arranged between the spacer elements and the surface of the component, and between the spacer elements and the surface of the electronic component.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Thomas Bemmerl, Joachim Mahler
  • Patent number: 10734352
    Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Irmgard Escher-Poeppel, Khalil Hosseini, Johannes Lodermeyer, Joachim Mahler, Thorsten Meyer, Georg Meyer-Berg, Ivan Nikitin, Reinhard Pufall, Edmund Riedl, Klaus Schmidt, Manfred Schneegans, Patrick Schwarz
  • Patent number: 10672678
    Abstract: In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: June 2, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Heinrich Koerner, Michael Bauer, Reimund Engl, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Publication number: 20200013749
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
    Type: Application
    Filed: September 17, 2019
    Publication date: January 9, 2020
    Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
  • Patent number: 10497634
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Heinrich Koerner, Michael Bauer, Reimund Engl, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Patent number: 10497694
    Abstract: A power semiconductor device includes a power transistor arranged in a power device region of a semiconductor substrate. The power semiconductor device further includes a first circuit arranged in a first circuit region of the semiconductor substrate. The power semiconductor device further includes a second circuit arranged in a second circuit region of the semiconductor substrate. The first circuit region is arranged at a first edge of the semiconductor substrate. The second circuit region is arranged at a second edge of the semiconductor substrate. The power device region is arranged between the first circuit region and the second circuit region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Guenther Kolmeder
  • Publication number: 20190348347
    Abstract: A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 14, 2019
    Inventors: Joachim Mahler, Giovanni Ragasa Garbin, Chen Wen Lee, Benjamin Reichert, Peter Strobel
  • Publication number: 20190341324
    Abstract: A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Inventors: Sook Woon CHAN, Chau Fatt CHIANG, Kok Yau CHUA, Soon Lock GOH, Swee Kah LEE, Joachim MAHLER, Mei Chin NG, Beng Keh SEE, Guan Choon Matthew Nelson TEE
  • Patent number: 10461056
    Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
  • Publication number: 20190287907
    Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.
    Type: Application
    Filed: February 19, 2019
    Publication date: September 19, 2019
    Applicant: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg, Guenter Tutsch
  • Publication number: 20190287875
    Abstract: In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Heinrich Koerner, Michael Bauer, Reimund ENGL, Michael Huettinger, Werner Kanert, Joachim Mahler, Brigitte Ruehle
  • Patent number: 10403556
    Abstract: A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Peter Irsigler, Joachim Mahler, Guenther Ruhl, Hans-Joachim Schulze, Markus Zundel
  • Patent number: 10396015
    Abstract: A semiconductor device includes a carrier, a semiconductor die and a die attach material arranged between the carrier and the semiconductor die. A fillet height of the die attach material is less than about 95% of a height of the semiconductor die. A maximum extension of the die attach material over edges of a main surface of the semiconductor die facing the die attach material is less than about 200 micrometers.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Benjamin Reichert, Chen Wen Lee, Giovanni Ragasa Garbin, Peter Strobel
  • Patent number: 10396007
    Abstract: A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: August 27, 2019
    Assignee: Infineon Technologies AG
    Inventors: Sook Woon Chan, Chau Fatt Chiang, Kok Yau Chua, Soon Lock Goh, Swee Kah Lee, Joachim Mahler, Mei Chin Ng, Beng Keh See, Guan Choon Matthew Nelson Tee
  • Patent number: 10297564
    Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg
  • Publication number: 20190109112
    Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.
    Type: Application
    Filed: October 5, 2017
    Publication date: April 11, 2019
    Inventors: Joachim Mahler, Georg Meyer-Berg