Abstract: A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Abstract: A device includes a semiconductor material having a first surface. A first material is applied to the first surface and a fiber material is embedded in the first material.

Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.

Abstract: An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer.

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

Abstract: A system and method for manufacturing an electric device package are disclosed. An embodiment comprises a carrier, a component disposed on the carrier, the component having a first component contact pad, and a first electrical connection between the first component contact pad and a first carrier contact pad, wherein the first electrical connection comprises a first hollow space, the first hollow space comprising a first liquid.

Abstract: Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity.

Abstract: A method for manufacturing a chip package is provided. The method including: holding a carrier including a plurality of dies; forming a separation between the plurality of dies by removing from the carrier one or more portions of the carrier between the plurality of dies; forming an encapsulation material in the removed one or more portions between the plurality of dies; separating the dies through the encapsulation material.

Abstract: In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.

Abstract: A connection element is arranged on a connection area of a semiconductor component. The connection element includes at least one bonding wire portion fixed on the connection area. The connection area is covered by an electrically conductive material, the fixed bonding wire portion being surrounded or embedded by the electrically conductive material.

Abstract: A method for attaching a metal surface to a carrier is provided, the method including: depositing a porous layer over at least one of a metal surface and a side of a carrier; and attaching the at least one of a metal surface and a side of a carrier to the porous layer by bringing a material into pores of the porous layer, resulting in the material forming an interconnection between the metal surface and the carrier.

Abstract: In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer.

Abstract: A method and a system for a reliable LED semiconductor device are provided. In one embodiment, the device comprises a carrier, a light emitting diode disposed on the carrier, an encapsulating material disposed over the light emitting diode and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.

Abstract: The electronic module includes a first carrier and a first semiconductor chip arranged on the first carrier. A second semiconductor chip is arranged above the first semiconductor chip. A material layer adheres the second semiconductor chip to the first carrier and encapsulates the first semiconductor chip.

Abstract: In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate.

Abstract: A chip arrangement is provided, the chip arrangement including: a first chip carrier; a second chip carrier; a first chip electrically connected to the first chip carrier; a second chip disposed over the first chip carrier and electrically insulated from the first chip carrier; and a third chip electrically connected to the second chip carrier; wherein at least one of the first chip and the second chip is electrically connected to the third chip.

Abstract: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

Abstract: A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Abstract: In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant.