Abstract: A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation element to be operated on the chip. In which case, as soon as the isolation information item is present for an isolation element, a one-time operation on the isolation element is begun.

Abstract: The present invention relates to conjugates of synthetic binding units and nucleic acids. The present invention also relates to methods for sorting and immobilizing nucleic acids on support materials using such conjugates by specific molecular addressing of the nucleic acids mediated by the synthetic binding systems. Particularly, the present invention also relates to novel methods of utilizing conjugates of synthetic binding units and nucleic acids to in active electronic array systems to produce novel array constructs from the conjugates, and the use of such constructs in various nucleic acid assay formats. In addition, the present invention relates to various novel forms of such conjugates, improved methods of making solid phase synthesized conjugates, and improved methods of conjugating pre-synthesized synthetic binding units and nucleic acids.

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: The invention relates to a novel method for the production of CNA oligomers and to artificial supramolecular CNA-p-RNA pairing systems and to the use thereof, especially in biotechnological assays.

Abstract: A test configuration for the functional testing of a semiconductor chip is described. The semiconductor chip, which can be subjected to a functional test for the purpose of checking the functionality of the semiconductor chip, is disposed on a support material. The semiconductor chip contains a self-test unit for generating test information and for carrying out the functional test. An energy source serves for providing an electrical energy supply from energy that is fed in contactlessly. The energy source is disposed on the support material and is connected to the semiconductor chip for the purpose of providing an energy supply on the semiconductor chip. The test configuration makes it possible to carry out a contactless functional test and to reduce the test costs by virtue of high parallelism during the functional test of a plurality of semiconductor chips.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A lowermost layer of control chips carries on it layers of memory chips. The memory chips are contacted via looped-through contacts that reach from one side of the other side of the memory chips and they are driven by the control chips that contain the test circuit for the memory chips.

Abstract: This invention relates to attachment chemistries for binding macromolecules to a substrate surface or to other conjugation targets. More particularly, this invention relates to attachment chemistries involving branched or linear structures having one or more hydrazide attachment moieties for binding the macromolecules to a substrate surface, or for other conjugation reactions. Novel modifying reagents are provided for the introduction of protected hydrazide attachment moieties or precursor forms of such hydrazides to the macromolecule, either as a single hydrazide or as multiple hydrazides.

Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

Abstract: A method and a configuration for driving one-time operable isolation elements on a semiconductor chip store an item of isolation information for each isolation element to be operated on the chip. In which case, as soon as the isolation information item is present for an isolation element, a one-time operation on the isolation element is begun.

Abstract: A telescopically extendible focusing hood which improves the viewing of the LCD screen of a digital camera in bright surrounding light. The focusing hood can be fixed to the rear wall of the camera, surrounding the LCD screen. The focusing hood preferably has an anti-reflection-coated enlarging lens or glass disk which covers the entire cross-section of the focusing hood in parallel to the fixing plane. In its extended state, the focusing hood can be used with a single lens in the manner of a 35 mm camera finder. When the enlarging lens is pushed in, the focusing hood can be used with two lenses for assessing the image.

Abstract: A portable data storage configuration has a card base and a display device, the display device being fixed to the card base. The display device is only partially connected to the card base by the fixed connection. This mounting technique results in that almost no lateral or shear forces act on the display device.

Abstract: The present invention relates to conjugates of synthetic binding units and nucleic acids. The present invention also relates to methods for sorting and immobilizing nucleic acids on support materials using such conjugates by specific molecular addressing of the nucleic acids mediated by the synthetic binding systems. Particularly, the present invention also relates to novel methods of utilizing conjugates of synthetic binding units and nucleic acids to in active electronic array systems to produce novel array constructs from the conjugates, and the use of such constructs in various nucleic acid assay formats. In addition, the present invention relates to various novel forms of such conjugates, improved methods of making solid phase synthesized conjugates, and improved methods of conjugating pre-synthesized synthetic binding units and nucleic acids.

Abstract: An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes addressable normal memory cells, a first redundancy unit having first addressable redundant memory cells and optically programmable switches for replacing an address of a defective normal memory cell by the address of a first redundant memory cell, and a second redundancy unit having second addressable redundant memory cells and electrically programmable switches for replacing an address of a defective normal memory cell by the address of a second redundant memory cell. The second redundancy unit can be connected by the activation of an irreversibly programmable switch, which enables a simplified functional test at the wafer level.

Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Abstract: A smart card contains a carrier body for receiving at least one system component, which has (in each case) a plurality of electrical components, and which unites the electrical functions for the operation of the smart card. The system component terminates approximately evenly with the top side of the card body of the smart card. At least one of the electrical components is accessible from the top side of the smart card.