Patents by Inventor Jochen Beintner

Jochen Beintner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200048072
    Abstract: A micromechanical sensor is described that includes: a substrate; a first functional layer that is situated on the substrate; a second functional layer that is situated on the first functional layer and that includes movable micromechanical structures; a cavity in the substrate that is situated below the movable mechanical structures; and a vertical trench structure that surrounds the movable micromechanical structures of the second functional layer and extends into the substrate down to the cavity.
    Type: Application
    Filed: September 25, 2017
    Publication date: February 13, 2020
    Inventors: Christoph Schelling, Jochen Beintner
  • Publication number: 20180346339
    Abstract: A polycrystalline material having low mechanical strain is provided. The polycrystalline material includes one or multiple layers of a first type and one or multiple layers of a second type. The layers of the first type and the layers of the second type each include at least one polycrystalline material component. The layers of the first type have a smaller average crystal grain size than the layers of the second type, a layer of the first type and a layer of the second type being situated, at least in part, one above the other in an alternating sequence, and it being the case for the transition between the layers of the first type and the layers of the second type to be abrupt or continuous.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 6, 2018
    Inventors: Andreas Hartlieb, Heiko Stahl, Jochen Beintner, Juergen Butz
  • Patent number: 9816920
    Abstract: A method for producing an integrated micromechanical fluid sensor component includes forming a first wafer with a first Bragg reflector and with a light-emitting device on a first substrate. The light-emitting device is configured to emit light rays in an emission direction from a surface of the light-emitting device facing away from the first Bragg reflector. The method further includes forming a second wafer with a second Bragg reflector and with a photodiode on a second substrate. The photodiode is arranged on a surface of the second Bragg reflector facing towards the second substrate. The method also includes bonding or gluing the first wafer to the second wafer such that there is formed a cavity into which a fluid is introduced and through which the light rays can pass. The method further includes separating the fluid sensor component from the first and the second wafer.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: November 14, 2017
    Assignee: Robert Bosch GmbH
    Inventors: Richard Fix, Rene Hartke, Jochen Beintner
  • Patent number: 9632123
    Abstract: A micromechanical structure, in particular a micromechanical electric field meter as a thunderstorm warning device, for detection of an electric field, comprising a substrate having a principal extension plane, a first electrode, a second electrode, and a drive assemblage for producing a relative motion of the second electrode with respect to the first electrode into an overlapping position, the first electrode and the second electrode being, in the overlapping position, disposed above one another in a projection direction extending perpendicularly to the principal extension plane of the substrate, wherein the second electrode has a defined potential for shielding the first electrode with respect to the electric field in the overlapping position.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: April 25, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventors: Lutz Mueller, Jochen Beintner
  • Publication number: 20160334329
    Abstract: A method for producing an integrated micromechanical fluid sensor component includes forming a first wafer with a first Bragg reflector and with a light-emitting device on a first substrate. The light-emitting device is configured to emit light rays in an emission direction from a surface of the light-emitting device facing away from the first Bragg reflector. The method further includes forming a second wafer with a second Bragg reflector and with a photodiode on a second substrate. The photodiode is arranged on a surface of the second Bragg reflector facing towards the second substrate. The method also includes bonding or gluing the first wafer to the second wafer such that there is formed a cavity into which a fluid is introduced and through which the light rays can pass. The method further includes separating the fluid sensor component from the first and the second wafer.
    Type: Application
    Filed: November 21, 2014
    Publication date: November 17, 2016
    Inventors: Richard Fix, Rene Hartke, Jochen Beintner
  • Patent number: 8963294
    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Thomas Ludwig, Edward Joseph Nowak
  • Publication number: 20140167732
    Abstract: A micromechanical structure, in particular a micromechanical electric field meter as a thunderstorm warning device, for detection of an electric field, comprising a substrate having a principal extension plane, a first electrode, a second electrode, and a drive assemblage for producing a relative motion of the second electrode with respect to the first electrode into an overlapping position, the first electrode and the second electrode being, in the overlapping position, disposed above one another in a projection direction extending perpendicularly to the principal extension plane of the substrate, wherein the second electrode has a defined potential for shielding the first electrode with respect to the electric field in the overlapping position.
    Type: Application
    Filed: December 9, 2013
    Publication date: June 19, 2014
    Inventors: Lutz MUELLER, Jochen Beintner
  • Patent number: 8614485
    Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li
  • Patent number: 7785944
    Abstract: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Bruce B. Doris, Xinlin Wang, Jochen Beintner, Ying Zhang, Philip J. Oldiges
  • Patent number: 7767562
    Abstract: A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: August 3, 2010
    Assignee: Qimonda AG
    Inventors: Helmut Horst Tews, Jochen Beintner
  • Patent number: 7737502
    Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Byeong Y. Kim
  • Patent number: 7696539
    Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Yujun Li, Kenneth T. Settlemyer, Jr., Jochen Beintner
  • Patent number: 7683428
    Abstract: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Jochen Beintner, Ramachandra Divakaruni
  • Patent number: 7666741
    Abstract: A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Yujun Li, Kenneth T. Settlemyer, Jr., Jochen Beintner
  • Publication number: 20090200604
    Abstract: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.
    Type: Application
    Filed: January 22, 2004
    Publication date: August 13, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dureseti Chidambarrao, Jochen Beintner, Ramachandra Divakaruni
  • Publication number: 20090101995
    Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
    Type: Application
    Filed: December 23, 2008
    Publication date: April 23, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li
  • Patent number: 7470570
    Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: December 30, 2008
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li
  • Publication number: 20080246059
    Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
    Type: Application
    Filed: June 18, 2008
    Publication date: October 9, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yujun Li, Kenneth T. Settlemyer, Jochen Beintner
  • Patent number: 7410844
    Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: August 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Yujun Li, Kenneth T. Settlemyer, Jr., Jochen Beintner
  • Publication number: 20080176365
    Abstract: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.
    Type: Application
    Filed: March 24, 2008
    Publication date: July 24, 2008
    Inventors: Huilong Zhu, Bruce B. Doris, Xinlin Wang, Jochen Beintner, Ying Zhang, Philip J. Oldiges