Patents by Inventor Jochen Beintner
Jochen Beintner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030186502Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.Type: ApplicationFiled: May 27, 2003Publication date: October 2, 2003Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
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Patent number: 6620676Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.Type: GrantFiled: June 29, 2001Date of Patent: September 16, 2003Assignee: International Business Machines CorporationInventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
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Patent number: 6607984Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.Type: GrantFiled: June 20, 2000Date of Patent: August 19, 2003Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Gill Yong Lee, Scott D. Halle, Jochen Beintner
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Patent number: 6602745Abstract: An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.Type: GrantFiled: January 31, 2002Date of Patent: August 5, 2003Assignee: Infineon Technologies North America Corp.Inventors: Peter Thwaite, Jochen Beintner
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Patent number: 6579759Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.Type: GrantFiled: August 23, 2002Date of Patent: June 17, 2003Assignees: International Business Machines Corporation, Infineon Technologies AGInventors: Michael Patrick Chudzik, Jochen Beintner, Ramachandra Divakaruni, Rajarao Jammy
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Patent number: 6579768Abstract: An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.Type: GrantFiled: January 31, 2002Date of Patent: June 17, 2003Assignee: Infineon Technologies North America Corp.Inventors: Peter Thwaite, Jochen Beintner
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Patent number: 6566228Abstract: Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.Type: GrantFiled: February 26, 2002Date of Patent: May 20, 2003Assignees: International Business Machines Corporation, Infineon TechnologiesInventors: Jochen Beintner, Rama Divakaruni, Jack A. Mandelman, Andreas Knorr
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Patent number: 6548344Abstract: In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to the pad nitride strip, so that after pad nitride removal, the poly is etched back and nitride is deposited conformal followed by anisotropic nitride RIE etch, so that the oxide protects the nitride underneath from being etched.Type: GrantFiled: November 16, 2001Date of Patent: April 15, 2003Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Jochen Beintner, Stephan Kudelka, Thomas Dyer
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Publication number: 20030062568Abstract: Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a predetermined depth into the recess without etching the inner material, resulting in the formation of a divot at the top of the trench. The divot is filled with an insulating material so that if source drain contacts are misaligned, the spacer serves to insulate the gate electrode from the contacts.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventor: Jochen Beintner
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Patent number: 6534369Abstract: An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.Type: GrantFiled: January 31, 2002Date of Patent: March 18, 2003Assignee: Infineon Technologies AGInventors: Peter Thwaite, Jochen Beintner
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Publication number: 20030003653Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.Type: ApplicationFiled: June 29, 2001Publication date: January 2, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
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Patent number: 6429092Abstract: A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench in a silicon substrate, and depositing and recessing a nitride liner in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar in the trench.Type: GrantFiled: June 19, 2000Date of Patent: August 6, 2002Assignee: Infineon Technologies AGInventors: Jochen Beintner, Alexander Michaelis, Ulrike Gruening, Oswald Spindler, Zvonimir Gabric
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Publication number: 20020094650Abstract: An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.Type: ApplicationFiled: January 31, 2002Publication date: July 18, 2002Inventors: Peter Thwaite, Jochen Beintner
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Publication number: 20020094618Abstract: An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.Type: ApplicationFiled: January 31, 2002Publication date: July 18, 2002Inventors: Peter Thwaite, Jochen Beintner
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Publication number: 20020079528Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.Type: ApplicationFiled: January 14, 2002Publication date: June 27, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION AND INFINEON TECHNOLOGIES NORTH AMERICA CORPORATIONInventors: Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary Bronner
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Publication number: 20020072179Abstract: An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.Type: ApplicationFiled: January 31, 2002Publication date: June 13, 2002Inventors: Peter Thwaite, Jochen Beintner
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Patent number: 6369419Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.Type: GrantFiled: June 23, 2000Date of Patent: April 9, 2002Assignee: International Business Machines CorporationInventors: Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary Bronner
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Patent number: 6352893Abstract: A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.Type: GrantFiled: June 3, 1999Date of Patent: March 5, 2002Assignee: Infineon Technologies AGInventors: Alexander Michaelis, Stephan Kudelka, Jochen Beintner, Oliver Genz
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Patent number: 6348394Abstract: A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.Type: GrantFiled: May 18, 2000Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Rama Divakaruni, Herbert Ho, Giuseppe La Rosa, Yujun Li, Jochen Beintner, Radhika Srinivasan
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Patent number: 6329271Abstract: A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.Type: GrantFiled: June 6, 2000Date of Patent: December 11, 2001Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Hiroyuki Akatsu, Yujun Li, Jochen Beintner