Patents by Inventor Jochen Beintner

Jochen Beintner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6893911
    Abstract: A process for fabricating integrated circuits is disclosed. In particular, the process includes rounding corners of the active regions. In one embodiment, a substrate prepared with a support region having an active area between first and second trench isolations. The top surfaces of the trench isolations extend above the surface of the substrate. First and second etch stop layers are deposited on the substrate, lining the substrate surface and trench isolations without filling the gap. The etch stop layers can be etched selective to each other and layers beneath and or above. The second etch stop layer includes horizontal and vertical portions. An etch selectively removes the vertical portions of the etch stop layer. An isotropic etch is then performed, removing exposed portions of the first etch stop layer. The second etch stop layer acts as an etch mask. The etch also creates an undercut beneath the second etch stop layer, exposing edge portions of the active area.
    Type: Grant
    Filed: March 16, 2003
    Date of Patent: May 17, 2005
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventor: Jochen Beintner
  • Publication number: 20050079730
    Abstract: An isolation trench formed in a semiconductor substrate and is filled with at least one insulating liner layer that is deposited along sidewalls and a bottom region of the isolation trench and with at least one silicon liner layer that is deposited atop the insulating liner layer. An upper portion of the insulating liner layers are removed, and the silicon liner layers are removed. A remaining portion of the trench is filled with another insulating layer.
    Type: Application
    Filed: October 10, 2003
    Publication date: April 14, 2005
    Applicant: Infineon Technologies North America Corp.
    Inventors: Jochen Beintner, Andreas Knorr
  • Patent number: 6853025
    Abstract: A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: February 8, 2005
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventors: Helmut Tews, Jochen Beintner, Stephan Kudelka
  • Publication number: 20040241939
    Abstract: A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Applicants: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Jochen Beintner, Naim Moumen, Porshia S. Wrschka
  • Publication number: 20040222498
    Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.
    Type: Application
    Filed: May 6, 2003
    Publication date: November 11, 2004
    Applicants: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Shane Wrschka
  • Publication number: 20040188740
    Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide.
    Type: Application
    Filed: October 17, 2003
    Publication date: September 30, 2004
    Applicants: International Business Machines Corp., Infineon Technologies North America Corp.
    Inventors: Jochen Beintner, Wolfgang Bergner, Richard A. Conti, Andreas Knorr, Rolf Weis
  • Publication number: 20040180547
    Abstract: A process for fabricating integrated circuits is disclosed. In particular, the process includes rounding corners of the active regions. In one embodiment, a substrate prepared with a support region having an active area between first and second trench isolations. The top surfaces of the trench isolations extend above the surface of the substrate. First and second etch stop layers are deposited on the substrate, lining the substrate surface and trench isolations without filling the gap. The etch stop layers can be etched selective to each other and layers beneath and or above. The second etch stop layer includes horizontal and vertical portions. An etch selectively removes the vertical portions of the etch stop layer. An isotropic etch is then performed, removing exposed portions of the first etch stop layer. The second etch stop layer acts as an etch mask. The etch also creates an undercut beneath the second etch stop layer, exposing edge portions of the active area.
    Type: Application
    Filed: March 16, 2003
    Publication date: September 16, 2004
    Inventor: Jochen Beintner
  • Patent number: 6790739
    Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
  • Publication number: 20040173858
    Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 9, 2004
    Inventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
  • Publication number: 20040164313
    Abstract: A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.
    Type: Application
    Filed: February 20, 2003
    Publication date: August 26, 2004
    Inventors: Helmut Tews, Jochen Beintner, Stephan Kudelka
  • Patent number: 6770526
    Abstract: A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: August 3, 2004
    Assignees: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Michael P. Chudzik, Jochen Beintner, Joseph F. Shepard, Jr.
  • Patent number: 6759291
    Abstract: A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: July 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier, Gary Bronner
  • Publication number: 20040110380
    Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 10, 2004
    Applicants: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Jochen Beintner, Laertis Economikos, Michael Wise, Andreas Knorr
  • Patent number: 6746933
    Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: June 8, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Rama Divakaruni, Johnathan Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Byeong Kim, Mihel Seitz, Akira Sudo, Yoichi Takegawa
  • Publication number: 20040095896
    Abstract: A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.
    Type: Application
    Filed: November 14, 2002
    Publication date: May 20, 2004
    Inventors: Michael P. Chudzik, Jochen Beintner, Joseph F. Shepard
  • Patent number: 6677205
    Abstract: Alignment tolerance for a vertical gate transistor device can be relaxed because of a spacer formed adjacent the trench. The gate electrode is formed of two materials that have etch selectivity between them, such that the outer material can be etched a predetermined depth into the recess without etching the inner material, resulting in the formation of a divot at the top of the trench. The divot is filled with an insulating material so that if source drain contacts are misaligned, the spacer serves to insulate the gate electrode from the contacts.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 13, 2004
    Assignee: Infineon Technologies AG
    Inventor: Jochen Beintner
  • Patent number: 6667504
    Abstract: The invention provides a trench storage structure that includes a substrate having a trench, a capacitor conductor in the lower part of the trench, a conductive node strap in the trench adjacent the capacitor conductor, a trench top oxide above the capacitor conductor, and a conductive buried strap in the substrate adjacent the trench top oxide. The trench top oxide includes a doped trench top oxide layer above the conductive strap, and an undoped trench top oxide layer above the doped trench top oxide layer.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: December 23, 2003
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corporation
    Inventors: Jochen Beintner, Wolfgang Bergner, Richard A. Conti, Andreas Knorr, Rolf Weis
  • Publication number: 20030186502
    Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
    Type: Application
    Filed: May 27, 2003
    Publication date: October 2, 2003
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
  • Patent number: 6620676
    Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: Rajeev Malik, Larry Nesbit, Jochen Beintner, Rama Divakaruni
  • Patent number: 6607984
    Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: August 19, 2003
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: Gill Yong Lee, Scott D. Halle, Jochen Beintner