Abstract: In order to detect light with in particular a high blue component, the inversion zone and the space charge zone of a CMOS-like structure are used. In conjunction with an at least partly transparent gate electrode, in particular a transparent conductive oxide or a patterned gate electrode, it becomes possible to absorb the short-wave component of incident light within the inversion zone and to reliably conduct away the generated charge carrier pairs to first and second contacts. During operation, a control voltage is applied to the gate electrode with a magnitude that generates a continuous inversion zone below the optionally patterned gate electrode.

Abstract: The photodiode has a p-type doped region (2) and an n-type doped region (3) in a semiconductor body (1), and a pn junction (4) between the p-type doped region and the n-type doped region. The semiconductor body has a cavity (5) such that the pn junction (4) has a distance (d) of at most 30 ?m from the bottom of the cavity (7).

Abstract: A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.

Abstract: In an insulation layer of an SOI substrate, a connection pad is arranged. A contact hole opening above the connection pad is provided on side walls and on the connection pad with a metallization that is contacted on top side with a top metal.

Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate.

Abstract: A substrate (1) of semiconductor material is provided with a contact pad (7). An opening (9) is formed through the semiconductor material from an upper surface to the contact pad, the opening forming an edge (18) at or near the upper surface. A dielectric layer (10) is applied on the semiconductor material in the opening. A metallization (11) is applied, which contacts the contact pad and is separated from the substrate by the dielectric layer. A top-metal (12) is applied, which contacts the metallization at or near the edge. A protection layer (13) is applied, which covers the top-metal and/or the metallization at least at or near the edge, and a passivation (15) is applied.

Abstract: An opening (9) is made in the substrate (1) over a terminal pad (7). A dielectric layer (10), a metallization (11), a compensation layer (13) and a passivation layer (15) are deposited so that the passivation layer is separated from the metallization by the compensation layer at least within the opening. A material that is suitable for reducing a mechanical stress between the metallization and the passivation layer is chosen for the compensation layer.

Abstract: Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24).

Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.

Abstract: A substrate (1) of semiconductor material is provided with a contact pad (7). An opening (9) is formed through the semiconductor material from an upper surface to the contact pad, the opening forming an edge (18) at or near the upper surface. A dielectric layer (10) is applied on the semiconductor material in the opening. A metallization (11) is applied, which contacts the contact pad and is separated from the substrate by the dielectric layer. A top-metal (12) is applied, which contacts the metallization at or near the edge. A protection layer (13) is applied, which covers the top-metal and/or the metallization at least at or near the edge, and a passivation (15) is applied.

Abstract: A light-sensitive component which has a semiconductor junction between a thin relatively highly doped epitaxial layer and a relatively lightly doped semiconductor substrate. Outside a light incidence window, an insulating layer is arranged between epitaxial layer and semiconductor substrate. In this case, the thickness of the epitaxial layer is less than 50 nm, with the result that a large proportion of the light quanta incident in the light incidence window can be absorbed in the lightly doped semiconductor substrate.

Abstract: A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of which additional doping the pn junction is shifted deeper into the substrate (SU). With the greater distance of the pn junction from defects at phase boundaries that is achieved in this way, the dark current within the photodiode is reduced.

Abstract: In the insulation layer (2) of an SOI substrate (1), a connection pad (7) is arranged. A contact hole opening (9) above the connection pad is provided on side walls and on the connection pad with a metallization (11) that is contacted on the top side with a top metal (12).

Abstract: A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried zone, a second zone having a second conductivity type that is different from the first conductivity type and above the first zone, and a third zone having the first conductivity type that is above the second zone. The buried zone includes first and second implantation regions that are formed via first and second implantations that are performed using a mask. The buried zone, the first zone, the second zone and the third zone are parts of a first transistor structure.

Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.

Abstract: An opening (9) is made in the substrate (1) over a terminal pad (7). A dielectric layer (10), a metallization (11), a compensation layer (13) and a passivation layer (15) are deposited so that the passivation layer is separated from the metallization by the compensation layer at least within the opening. A material that is suitable for reducing a mechanical stress between the metallization and the passivation layer is chosen for the compensation layer.

Abstract: A photodiode in which a pn junction is formed between the doped region (DG) formed in the surface of a crystalline semiconductor substrate and a semiconductor layer (HS) deposited above said doped region. An additional doping (GD) is provided in the edge region of the doped zone, by means of which additional doping the pn junction is shifted deeper into the substrate (SU). With the greater distance of the pn junction from defects at phase boundaries that is achieved in this way, the dark current within the photodiode is reduced.

Abstract: A transistor includes an emitter, a collector, and a base layer having a base contact. The base layer includes an intrinsic region between the emitter and the collector, an extrinsic region between the intrinsic region and the base contact, and a first doping layer that is doped with a trivalent substance, that extends into the extrinsic region, and that is counter-doped with a pentavalent substance in a region adjacent to the emitter.

Abstract: For the production of an improved bipolar transistor comprising a low-resistance base terminal, a dielectric layer is deposited over the semiconductor substrate and is highly doped via an implantation mask. In a subsequent controlled thermal step, the dopant is then indiffused into the semiconductor substrate from the dielectric layer serving as a dopant repository. This gives rise to a low-resistance region with which the extrinsic base can be defined carefully.

Abstract: A light-sensitive component which has a semiconductor junction between a thin relatively highly doped epitaxial layer and a relatively lightly doped semiconductor substrate. Outside a light incidence window, an insulating layer is arranged between epitaxial layer and semiconductor substrate. In this case, the thickness of the epitaxial layer is less than 50 nm, with the result that a large proportion of the light quanta incident in the light incidence window can be absorbed in the lightly doped semiconductor substrate.