Patents by Inventor Jochen Kraft

Jochen Kraft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080272413
    Abstract: In order to detect light with in particular a high blue component, the inversion zone and the space charge zone of a CMOS-like structure are used. In conjunction with an at least partly transparent gate electrode, in particular a transparent conductive oxide or a patterned gate electrode, it becomes possible to absorb the short-wave component of incident light within the inversion zone and to reliably conduct away the generated charge carrier pairs to first and second contacts. During operation, a control voltage is applied to the gate electrode with a magnitude that generates a continuous inversion zone below the optionally patterned gate electrode.
    Type: Application
    Filed: January 26, 2006
    Publication date: November 6, 2008
    Inventors: Hubert Enichlmair, Jochen Kraft, Georg Rohrer
  • Publication number: 20070269953
    Abstract: For the production of an improved bipolar transistor comprising a low-resistance base terminal, a dielectric layer is deposited over the semiconductor substrate and is highly doped via an implantation mask. In a subsequent controlled thermal step, the dopant is then indiffused into the semiconductor substrate from the dielectric layer serving as a dopant repository. This gives rise to a low-resistance region with which the extrinsic base can be defined carefully.
    Type: Application
    Filed: January 19, 2005
    Publication date: November 22, 2007
    Inventors: Gerald Meinhardt, Jochen Kraft
  • Publication number: 20070224748
    Abstract: A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried zone, a second zone having a second conductivity type that is different from the first conductivity type and above the first zone, and a third zone having the first conductivity type that is above the second zone. The buried zone includes first and second implantation regions that are formed via first and second implantations that are performed using a mask. The buried zone, the first zone, the second zone and the third zone are parts of a first transistor structure.
    Type: Application
    Filed: March 16, 2007
    Publication date: September 27, 2007
    Applicant: Austriamicrosystems AG
    Inventors: Georg Rohrer, Bernhard Loffler, Jochen Kraft
  • Publication number: 20050127476
    Abstract: The invention relates to a transistor having an emitter (1), a collector (2), and a base layer (3), wherein the emitter (1) extends into the base layer (3), wherein the base layer (3) has an intrinsic region (4) arranged between the emitter (1) and the collector (2), and an extrinsic region (6) that runs between the intrinsic region (4) and a base contact (5), wherein the base layer (3) contains a first doping layer (7) doped with a trivalent doping substance, which extends into the extrinsic region (6) and which is counter-doped by means of a pentavalent counter-doping substance (8) in the region of the emitter (1). The electrical resistance of the base layer (3) can be reduced, in advantageous manner, by means of the first doping layer (7).
    Type: Application
    Filed: December 20, 2002
    Publication date: June 16, 2005
    Inventors: Jochen Kraft, Bernhard Loeffler, Georg Roerer
  • Patent number: 6562547
    Abstract: A method for producing structures in chips is realized by carrying out a sequence of structuring steps in a self-adjusting manner. By structuring a first auxiliary layer applied on a substrate, a first masking structure is formed after a first masking procedure, which first masking structure has at least one partial region projecting beyond the surface of the substrate. After this, a further structuring step is carried out, for instance, by etching, implantation or CVD, using the previously produced first masking structure as a mask. After this, the first masking structure with a view to forming a second masking structure is inverted by applying at least one second auxiliary layer onto the first masking structure. The thus formed structure is at least partially taken off and the thus denuded first auxiliary layer is selectively removed, whereupon the second masking structure is used as a mask for a further structuring step.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: May 13, 2003
    Assignee: Austria Mikro Systeme International Aktiengesellschaft
    Inventors: Jochen Kraft, Martin Schatzmayr, Hubert Enichlmair
  • Publication number: 20030044723
    Abstract: A method for producing structures in chips is realized by carrying out a sequence of structuring steps in a self-adjusting manner. By structuring a first auxiliary layer applied on a substrate, a first masking structure is formed after a first masking procedure, which first masking structure has at least one partial region projecting beyond the surface of the substrate. After this, a further structuring step is carried out, for instance, by etching, implantation or CVD, using the previously produced first masking structure as a mask. After this, the first masking structure with a view to forming a second masking structure is inverted by applying at least one second auxiliary layer onto the first masking structure. The thus formed structure is at least partially taken off and the thus denuded first auxiliary layer is selectively removed, whereupon the second masking structure is used as a mask for a further structuring step.
    Type: Application
    Filed: December 1, 2000
    Publication date: March 6, 2003
    Inventors: Jochen Kraft, Martin Schatzmayr, Hubert Enichlmair