Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

Abstract: A pedestal projection having reduced cross-sectional area secures a MEMs device to a housing surface in a manner which reduces strain on the MEMS die due to differences in coefficients of thermal expansion while more evenly distributing to the MEMS sensor any external forces mechanically coupled through the housing structure. The pedestal projection may be integrally formed with a surface on either MEMS die or housing member and is axially aligned with the structure which anchors the MEMS sensor to the MEMS die.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract: A method, apparatus and computer program product are provided in order to provide timely notification of a medical response service of a subject who may require medical assistance. In the context of a method, information regarding a subject is received from an interface system carried by a head worn device of the subject, such as a helmet worn by the subject. The information provided by the interface system is utilized for non-medical purposes. The method also determines whether the subject is considered to require medical assistance based upon the information regarding the subject. The method may also include causing notification of a medical response service of the subject in an instance in which the subject is considered to require medical assistance.

Abstract: Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as one or more of silicon nitride, silicon oxide, polysilicon, and titanium nitride structures. Selected etching solution compositions and processing conditions provide high etching selectivity of hafnium oxide relative to these other materials. As such, hafnium oxide structures may be partially or completely removed without significant damage to other exposed structures made from these other materials. In some embodiments, the etching rate hafnium oxide is two or more times greater than the etching rate of silicon oxide and/or twenty or more times greater that the etching rate of polysilicon. The etching rate of hafnium oxide may be one and half times greater than the etching rate of silicon nitride and/or five or more times greater than the etching rate of titanium nitride.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.

Abstract: A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

Abstract: A wireless connection between a mobile device and an IP-based wireless telecommunications network is established when the mobile device registers with a network controller (NC) through an access point (AP). When a geographical position is needed for the mobile device (e.g., a 911 call), messages are exchanged between the NC and a serving mobile location center (SMLC), where the SMLC retrieves information from a database that is used to identify the geographic position of the mobile device. The database can store a variety of information related to mobile devices such as: last known position, IP address, MAC address, a mobile or subscriber identifier (such as an International Mobile Subscriber Identity (IMSI)), last CGI, etc. The geographical position is communicated back to the NC, which can then forward the position information to a switch for processing such as for 911 calls.

Abstract: The present invention is directed to a system, method, and software product for ordering of digital photo services among a plurality order terminals each being associated with one of a plurality of business entities, using a digital image provided on a digital storage device associated with one of a plurality of digital storage device providers. The method includes maintaining information with respect to business relationships between the plurality of digital storage device providers and the plurality of business entities; providing a digital storage device at one of the order terminals; and providing an offering at the one order terminal based on a business relationship between the business entity associated with the one order terminal and the digital device provider associated with the digital storage device.

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

Abstract: Methods and systems for managing applications by an application manager within a man machine interface (MMI) application framework are disclosed. Aspects of the method may include creating an active application context upon launching a first application by the application manager. The active application context may be transitioned into a suspended application context upon suspending the first application by the application manager. The suspended application context may be stored in an application manager context stack. The stored suspended application context may be acquired from the application manager context stack upon receipt of an exit message by the application manager. The application manager context stack may comprise a last-in-first-out (LIFO) context stack. The first application associated with said suspended application context may be reactivated upon removal of the suspended application context from the application manager context stack.

Abstract: An apparatus for dispensing a frozen confection is provided comprising: an insulated chamber (1) housing a container (3) of a frozen confection; a refrigeration system (8); a nozzle (4) having an inner end which is connected to the container (3); and an outer end which is located outside the insulated chamber; means for applying pressure to the frozen confection thereby to dispense it from the container (3; a cap (7) which can enclose the outer end (6) of the nozzle (4) when closed and which allows external access to the outer end (6) of the nozzle (4) when open; and one or more channels (12) which allow cold air to flow from the chamber into the region around the outer end of the nozzle; wherein the apparatus comprises a removable holder (10) that supports the container (3) and wherein the spaces between the container (3), the inside of the chamber and the underside of the holder form the one or more channels (12).

Abstract: Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.

Abstract: Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: Methods and systems for processing text input within a man-machine interface (MMI) application framework are provided and may comprise creating at least one text editor by an active application and generating at least one text edit view by the text editor. Text input, for example, predictive input, multi-tap input and/or numeric input, which may be associated with the text edit view, may be received by the text editor. At least one text editor feature may be associated with at least one text editor and the text editor feature may comprise a maximum string length characteristic and/or a cursor characteristic. The text editor feature may be customized for each text editor view and the text input may be buffered by a buffer within the MMI application framework.

Abstract: A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack.