Patents by Inventor John C. Arnold
John C. Arnold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240065916Abstract: A patient securing overlay includes a sheet of fabric configured to support a patient's torso on a surgical table. The sheet of fabric includes friction enhancing elements applied to at least a portion of an upper surface. The sheet of fabric is attached near its side edges to two or more side flaps that extend laterally outward from the side edges of the sheet of fabric. Each of the side flaps is attached to the surgical table at two or more attachment points. A distance between adjacent attachment points is greater than a distance between an attachment point and the sheet of fabric in order to naturally create a favorable retaining force vector angle of less than 45° between the attachment point and the sheet of fabric.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Inventors: Scott D. Augustine, Ryan S. Augustine, Brent M. Augustine, Garrett J. Augustine, Susan D. Augustine, Randall C. Arnold, John R. Beckman, John J. Cardwell
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Patent number: 11404317Abstract: A method for fabricating a semiconductor device includes recessing a first odd hardmask and a first even hardmask to form recessed odd and even hardmasks, forming a first conductive hardmask including first conductive hardmask material on the recessed odd hardmask and a second conductive hardmask on the recessed even hardmask, and forming self-aligned vias at line ends corresponding to the first odd and even conductive lines based at least in part on the first and second conductive hardmasks.Type: GrantFiled: September 24, 2019Date of Patent: August 2, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Ashim Dutta, Dominik Metzler, Ekmini A. De Silva
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Publication number: 20220165612Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Inventors: John C. Arnold, Ashim Dutta, Dominik Metzler, Timothy M. Philip, Sagarika Mukesh
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Patent number: 11276607Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.Type: GrantFiled: September 13, 2019Date of Patent: March 15, 2022Assignee: International Business Machines CorporationInventors: John C. Arnold, Ashim Dutta, Dominik Metzler, Timothy M. Philip, Sagarika Mukesh
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Patent number: 11171002Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.Type: GrantFiled: February 24, 2020Date of Patent: November 9, 2021Assignee: Tessera, Inc.Inventors: John C. Arnold, Anuja E. DeSilva, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
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Patent number: 11133260Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.Type: GrantFiled: November 15, 2019Date of Patent: September 28, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chi-Chun Liu, John C. Arnold, Dominik Metzler, Nelson Felix, Ashim Dutta
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Publication number: 20210151377Abstract: A method of forming a self-aligned top via is provided. The method includes forming a metallization layer on a substrate, and forming a hardmask layer on the metallization layer. The method further includes forming a pair of adjacent parallel mandrels on the hardmask layer with sidewall spacers on opposite sides of each mandrel. The method further includes forming a planarization layer on the exposed portions of the hardmask layer, mandrels, and sidewall spacers, and forming an opening in the planarization layer aligned between the adjacent parallel mandrels. The method further includes forming a spacer layer in the opening, and removing portions of the spacer layer to form a pair of spacer plugs between sections of the sidewall spacers.Type: ApplicationFiled: November 15, 2019Publication date: May 20, 2021Inventors: Chi-Chun Liu, John C. Arnold, Dominik Metzler, Nelson Felix, Ashim Dutta
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Publication number: 20210090951Abstract: A method for fabricating a semiconductor device includes recessing a first odd hardmask and a first even hardmask to form recessed odd and even hardmasks, forming a first conductive hardmask including first conductive hardmask material on the recessed odd hardmask and a second conductive hardmask on the recessed even hardmask, and forming self-aligned vias at line ends corresponding to the first odd and even conductive lines based at least in part on the first and second conductive hardmasks.Type: ApplicationFiled: September 24, 2019Publication date: March 25, 2021Inventors: John C. Arnold, Ashim Dutta, Dominik Metzler, Ekmini A. De Silva
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Patent number: 10957850Abstract: A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer.Type: GrantFiled: October 4, 2018Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashim Dutta, Isabel Cristina Chu, Son Nguyen, Michael Rizzolo, John C. Arnold
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Publication number: 20210082746Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.Type: ApplicationFiled: September 13, 2019Publication date: March 18, 2021Inventors: John C. Arnold, Ashim Dutta, Dominik Metzler, Timothy M. Philip, Sagarika Mukesh
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Patent number: 10879068Abstract: A device and a method for forming the device is contemplated. The device and method include patterning a hardmask formed over a substrate. The hardmask is modified by raising an annealing temperature of the hardmask from a first annealing temperature to a second annealing temperature using ion implantation. The hardmask is annealed with a laser beam using a process temperature between the first annealing temperature and the second annealing temperature.Type: GrantFiled: May 9, 2018Date of Patent: December 29, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yongan Xu, Yann Mignot, John C. Arnold, Oleg Gluschenkov
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Patent number: 10833258Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.Type: GrantFiled: May 2, 2019Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, Karthik Yogendra, John C. Arnold
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Patent number: 10833257Abstract: Techniques are provided for fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.Type: GrantFiled: May 2, 2019Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Ashim Dutta, John C. Arnold, Chih-Chao Yang, Theodorus E. Standaert
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Publication number: 20200350495Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.Type: ApplicationFiled: May 2, 2019Publication date: November 5, 2020Inventors: Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, Karthik Yogendra, John C. Arnold
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Publication number: 20200350494Abstract: Techniques are provided for fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.Type: ApplicationFiled: May 2, 2019Publication date: November 5, 2020Inventors: Ashim Dutta, John C. Arnold, Chih-Chao Yang, Theodorus E. Standaert
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Publication number: 20200266066Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.Type: ApplicationFiled: February 24, 2020Publication date: August 20, 2020Applicant: TESSERA, INC.Inventors: John C. Arnold, Anuja E. DeSilva, Nelson M. Felix, Chi-Chun Liu, Yann A.M. Mignot, Stuart A. Sieg
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Patent number: 10714683Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.Type: GrantFiled: December 18, 2019Date of Patent: July 14, 2020Assignee: International Business Machines CorporationInventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold
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Patent number: 10707413Abstract: Techniques are provided for fabricating magnetic random-access memory devices, which eliminate junction shorts and minimize gouging of an underlying insulating layer. For example, a bottom electrode layer, a magnetic tunnel junction (MTJ) stack, and an upper electrode layer are formed over an insulating layer. The bottom electrode layer and the MTJ stack are etched to form an upper electrode and a MTJ structure. A cleaning etch process removes residual metallic material which is re-deposited on sidewalls of the MTJ structure as a result of etching the MTJ stack. A conformal dielectric layer is formed to encapsulate the upper electrode and the MTJ structure and prevent oxidation or re-deposition of metallic material on the cleaned sidewalls of the MTJ structure. A final etch process is performed to pattern the conformal dielectric layer and bottom electrode layer to form a spacer on sidewalls of the MTJ structure and form a bottom electrode.Type: GrantFiled: March 28, 2019Date of Patent: July 7, 2020Assignee: International Business Machines CorporationInventors: Ashim Dutta, Chih-Chao Yang, John C. Arnold, Michael Rizzolo, Jon Slaughter
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Patent number: 10685879Abstract: A method for fabricating a semiconductor device includes forming misalignment tolerant vias each having a landing area configured to account for alignment mismatch resulting from subsequent formation of conductive structures, depositing a conductive layer over the misalignment tolerant vias, and obtaining conductive layer patterning including each of the conductive structures formed on at least a portion of a respective one of the landing areas, including subtractively patterning the conductive layer. The misalignment tolerant vias and the conductive structures imparting a semiconductor device geometry accounting for the alignment mismatch.Type: GrantFiled: August 15, 2019Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: John C. Arnold, Ashim Dutta, Dominik Metzler, Takeshi Nogami
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Patent number: 10680169Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.Type: GrantFiled: June 13, 2018Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold