Patents by Inventor John C. Arnold
John C. Arnold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8580692Abstract: A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.Type: GrantFiled: June 29, 2011Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Sivananda K. Kanakasabapathy, Stefan Schmitz, Yunpeng Yin
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Patent number: 8536630Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: GrantFiled: November 21, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Xuefeng Hua, Rangarajan Jagannathan, Stefan Schmitz
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Patent number: 8536031Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.Type: GrantFiled: February 19, 2010Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrer, Steven J. Holmes, Pushkara Varanasi
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Publication number: 20130216776Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.Type: ApplicationFiled: February 22, 2012Publication date: August 22, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Sean D. Burns, Steven J. Holmes, David V. Horak, Muthumanickam Sankarapandian, Yunpeng Yin
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Patent number: 8481423Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: GrantFiled: September 19, 2007Date of Patent: July 9, 2013Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Patent number: 8470706Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: GrantFiled: September 1, 2012Date of Patent: June 25, 2013Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Patent number: 8470711Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.Type: GrantFiled: November 23, 2010Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, Steven J. Holmes, Yunpeng Yin
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Patent number: 8464397Abstract: A self-affixing, removable, one-piece handle can be applied and removed from an item, such as a shopping cart, stroller, or the like, or the handle can be applied and removed from any number of items, such as the shoulder straps of a diaper bag or the loop handles of a set of shopping bags, or the like. By being self-affixing, the handle may be attached and removed from the item without the need for tools or any additional items, such as clamps, screws, adhesive, or the like. The handle may provide a link between the shopping cart or stroller and a child. Typical shopping carts or strollers do not provide a suitable location for a child to hold onto while walking alongside. Moreover, a separate, removable, self-affixing handle may be useful to help limit the spread of germs by allowing each child to have their own personal handle.Type: GrantFiled: March 1, 2010Date of Patent: June 18, 2013Inventors: John C. Arnold, IV, Stephanie Arnold
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Patent number: 8448103Abstract: A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.Type: GrantFiled: February 1, 2011Date of Patent: May 21, 2013Assignees: International Business Machines Corporation, Globalfoundries, Inc.Inventors: John C. Arnold, Catherine Labelle
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Patent number: 8383483Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: GrantFiled: August 14, 2009Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: John C. Arnold, Glenn A. Biery, Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Bruce B. Doris, Michael A. Gribelyuk, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Joseph S. Newbury, Vamsi K. Paruchuri, Michelle L. Steen
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Publication number: 20130026639Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.Type: ApplicationFiled: September 14, 2012Publication date: January 31, 2013Applicant: International Business Machines CorporationInventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrar, Steven J. Holmes, Pushkara Varanasi
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Publication number: 20130001749Abstract: A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask and a large feature (FX) mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; and etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: JOHN C. ARNOLD, Sivananda K. Kanakasabapathy, Stefan Schmitz, Yunpeng Yin
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Publication number: 20130001750Abstract: A method for formation of a fin field effect transistor (FinFET) device includes forming a mandrel mask on a metal hardmask layer of a film stack, the film stack including a silicon on insulator (SOI) layer located underneath the metal hardmask layer; forming a large feature (FX) mask on the metal hardmask layer; etching the mandrel mask and the FX mask simultaneously into the metal hardmask layer; etching the mandrel mask and the FX mask into the SOI layer using the etched metal hardmask layer as a mask.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: International Business Machines corporationInventors: JOHN C. ARNOLD, Sivananda K. Kanakasabapathy, Stefan Schmitz, Yunpeng Yin
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Publication number: 20120329269Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: ApplicationFiled: September 1, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Publication number: 20120329272Abstract: A method for forming small dimension openings in the organic masking layer of tri-layer lithography. The method includes forming an organic polymer layer over a semiconductor substrate; forming a silicon containing antireflective coating on the organic polymer layer; forming a patterned photoresist layer on the antireflective coating, the patterned photoresist layer having an opening therein; performing a first reactive ion etch to transfer the pattern of the opening into the antireflective coating to form a trench in the antireflective coating, the organic polymer layer exposed in a bottom of the trench; and performing a second reactive ion etch to extend the trench into the organic polymer layer, the second reactive ion etch forming a polymer layer on sidewalls of the trench, the second reactive ion etch containing a species derived from a gaseous hydrocarbon.Type: ApplicationFiled: June 23, 2011Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Jennifer Schuler, Yunpeng Yin
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Publication number: 20120282779Abstract: A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.Type: ApplicationFiled: May 6, 2011Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, David V. Horak, Yunpeng Yin
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Patent number: 8298954Abstract: A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.Type: GrantFiled: May 6, 2011Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, David V. Horak, Yunpeng Yin
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Publication number: 20120244711Abstract: An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.Type: ApplicationFiled: March 23, 2011Publication date: September 27, 2012Applicant: International Business Machines CorporationInventors: Yunpeng Yin, John C. Arnold, Matthew E. Colburn, Sean D. Burns
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Publication number: 20120198403Abstract: A methodology for varying the depth of a design feature on a semiconductor wafer. Vias are formed according to design requirements. Nonfunctioning vias may also be placed at a location with respect to a design feature. After vias are formed, the semiconductor wafer is caused to undergo an ashing process followed by the application of an organic planarizing layer. The design features are then formed. If the depth of the design features does not meet design requirements, another semiconductor wafer may be processed to meet design requirements by varying the ashing conditions, choice of organic planarizing layer and/or the nonfunctioning and/or functioning via placement. Design features having various depths on a single semiconductor wafer may be formed with a single lithographic process.Type: ApplicationFiled: February 1, 2011Publication date: August 2, 2012Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Catherine Labelle
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Publication number: 20120126358Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, Steven J. Holmes, Yunpeng Yin