Patents by Inventor John C. Arnold
John C. Arnold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120061684Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Xuefeng Hua, Rangarajan Jagannathan, Stefan Schmitz
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Patent number: 8129843Abstract: Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.Type: GrantFiled: August 10, 2010Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: John C. Arnold, Sampath Purushothaman, Muthumanickam Sankarapandian, Hosadurga K. Shobha, Terry A. Spooner
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Patent number: 8119531Abstract: A method of forming a trench is provided that includes providing a stack having a semiconductor layer or dielectric layer, a metal nitride layer, a leveling layer, and a first mask layer. First trenches are etched through the first mask layer and the leveling layer. The first mask layer is removed. A second mask layer is formed on the leveling layer. Second trenches are formed through the second mask layer, wherein the base of the second trenches do not extend through the metal nitride layer. The second mask layer is removed. Exposed portions of the metal nitride layer are etched selectively to the semiconductor layer and remaining portions of the leveling layer to extend the first trenches and the second trenches into contact with an upper surface of the semiconductor layer.Type: GrantFiled: January 26, 2011Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, Yunpeng Yin
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Patent number: 8084329Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: GrantFiled: January 26, 2010Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: John C. Arnold, Xuefeng Hua, Rangarajan Jagannathan, Stefan Schmitz
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Publication number: 20110204523Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.Type: ApplicationFiled: February 19, 2010Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrer, Steven J. Holmes, Pushkara Varanasi
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Patent number: 7880241Abstract: A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.Type: GrantFiled: February 23, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: John C. Arnold, Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana
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Publication number: 20110015856Abstract: A fuel information data service system is presented. In exemplary embodiments of the present invention a fuel information data service can include a controller operable to receive information regarding costs of various types of fuel, and to correlate such costs of fuel information to actual operating costs for a given vehicle, based on a known consumption efficiency for a plurality of types of fuel for that vehicle, to calculate a FuelEQ or fuel equivalency for each fuel offering. In exemplary embodiments of the present invention an exemplary system can further include a presentation device coupled to the controller where the controller is further operable to present such FuelEQ information expressed as a cost per distance traveled.Type: ApplicationFiled: July 19, 2010Publication date: January 20, 2011Applicants: XM Satellite Radio, Inc., Sirius XM Radio, Inc.Inventor: John C. Arnold
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Publication number: 20100320617Abstract: Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.Type: ApplicationFiled: August 10, 2010Publication date: December 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Sampath Purushothaman, Muthumanickam Sankarapandian, Hosadurga K. Shobha, Terry A. Spooner
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Publication number: 20100293754Abstract: A self-affixing, removable, one-piece handle can be applied and removed from an item, such as a shopping cart, stroller, or the like, or the handle can be applied and removed from any number of items, such as the shoulder straps of a diaper bag or the loop handles of a set of shopping bags, or the like. By being self-affixing, the handle may be attached and removed from the item without the need for tools or any additional items, such as clamps, screws, adhesive, or the like. The handle may provide a link between the shopping cart or stroller and a child. Typical shopping carts or strollers do not provide a suitable location for a child to hold onto while walking alongside. Moreover, a separate, removable, self-affixing handle may be useful to help limit the spread of germs by allowing each child to have their own personal handle.Type: ApplicationFiled: March 1, 2010Publication date: November 25, 2010Inventors: John C. Arnold, IV, Stephanie Arnold
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Patent number: 7781332Abstract: Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.Type: GrantFiled: September 19, 2007Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: John C. Arnold, Sampath Purushothaman, Muthumanickam Sankarapandian, Hosadurga K. Shobha, Terry A. Spooner
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Patent number: 7776695Abstract: A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.Type: GrantFiled: January 9, 2006Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: John C. Arnold, Dureseti Chidambarrao, Ying Li, Rajeev Malik, Shreesh Narasimha, Siddhartha Panda, Brian L. Tessier, Richard Wise
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Publication number: 20100187579Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: ApplicationFiled: January 26, 2010Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JOHN C. ARNOLD, XUEFENG HUA, RANGARAJAN JAGANNATHAN, STEFAN SCHMITZ
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Publication number: 20100041221Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: ApplicationFiled: August 14, 2009Publication date: February 18, 2010Applicant: International Business Machines CoporationInventors: John C. Arnold, Glenn A. Biery, Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Bruce B. Doris, Michael A. Gribelyuk, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Joseph S. Newbury, Vamsi K. Paruchuri, Michelle L. Steen
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Publication number: 20090075472Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: ApplicationFiled: September 19, 2007Publication date: March 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Publication number: 20090072401Abstract: Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.Type: ApplicationFiled: September 19, 2007Publication date: March 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Sampath Purushothaman, Muthumanickam Sankarapandian, Hosadurga K. Shobha, Terry A. Spooner
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Publication number: 20080203447Abstract: A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.Type: ApplicationFiled: February 23, 2007Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana
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Publication number: 20070285513Abstract: An emulator of the type suitable to simulate connection of an intended device to another device in the absence of an actual connection therebetween. The emulator may be configured to simulate any number of connections, such as but not limited to printer port, display port, and scale port connection. The emulator may be used with any number of elements, such as but not limited to point of sale (POS) device. The emulator may be configured to receive data from the port, and optionally, to transmit the received data to remote locations, such as through network communications.Type: ApplicationFiled: June 13, 2006Publication date: December 13, 2007Applicant: Image Vault, LLCInventor: John C. Arnold
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Publication number: 20070267618Abstract: A phase change memory cell includes a first spacer electrically coupled to a first electrode and to a second spacer. The first spacer includes a planar base contacting the first electrode and a wall extending from the planar base. The second spacer is electrically coupled between a second electrode and the wall of the first spacer. The phase change memory cell is formed at a boundary where the wall of the first spacer contacts the second spacer.Type: ApplicationFiled: May 17, 2006Publication date: November 22, 2007Inventors: Shoaib Zaidi, John C. Arnold
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Publication number: 20070158753Abstract: A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.Type: ApplicationFiled: January 9, 2006Publication date: July 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Dureseti Chidambarrao, Ying Li, Rajeev Malik, Shreesh Narasimha, Siddhartha Panda, Brian L. Tessier, Richard Wise
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Patent number: 6500315Abstract: A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).Type: GrantFiled: August 3, 2000Date of Patent: December 31, 2002Assignee: Motorola, Inc.Inventors: Valli Arunachalam, Peter L. G. Ventzek, Dean J. Denning, John C. Arnold