Patents by Inventor John D. Hyde
John D. Hyde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9064196Abstract: An RFID tag is configured to adjust its current clock frequency to conserve tag power while receiving a reader signal and/or backscattering a signal. The tag may determine whether to adjust its current clock frequency based on one or more timing parameters, which may be determined from a reader command and/or from a signal to be backscattered. The counting rate and/or limit of a tag counter and/or the power supplied to a tag component may also be adjusted. The current tag clock frequency may be adjusted during the signal reception/backscattering process and optionally restored once the process is completed.Type: GrantFiled: May 2, 2012Date of Patent: June 23, 2015Assignee: Impinj, Inc.Inventors: Vadim Gutnik, Scott A. Cooper, John D. Hyde, Theron Stanford
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Patent number: 9031504Abstract: RFID tags, tag circuits, and methods are provided that reject at least in part the distortion caused to wireless signals by interference in the environment. When the received RF wave is converted into an unfiltered input (971), a filtered output (972) is generated that does not include an artifact feature deriving from the distortion. The filtered output is used instead of the unfiltered input, which results in tag operation as if there were less interference in the environment, or none at all.Type: GrantFiled: October 29, 2013Date of Patent: May 12, 2015Assignee: Impinj, Inc.Inventors: John D. Hyde, Kurt E. Sundstrom
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Patent number: 8952792Abstract: A tuning circuit in an RFID tag may be used to match antenna and integrated circuit (IC) impedances to maximize the efficiency of IC power extraction from an incident RF wave. The tuning circuit, which requires less power to operate than the IC, adjusts a variable impedance to improve the impedance matching between the IC and the tag antenna and thereby increase the IC power extraction efficiency. The IC may begin operating according to a protocol when it extracts sufficient power from the RF wave or when an optimal impedance matching and power transfer is achieved.Type: GrantFiled: January 6, 2012Date of Patent: February 10, 2015Assignee: Impinj, Inc.Inventors: Shailendra Srinivas, Jay Kuhn, Ronald A. Oliver, John D. Hyde, Christopher J. Diorio
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Patent number: 8635718Abstract: A single-bowl sink is converted into double-bowl sink by a specially designed divider plate placed across the inner walls of the sink. Each bowl (basin) has one drain hole for drainage of liquid and has top surface, a bottom surface and a pair of strips of ferrous metal attached to the bottom surface of the basin. The divider plate has an upper edge and a lower edge and a channel inside the lower edge, a permanent magnet in said channel for providing magnetic attraction between the divider plate and the strips of ferrous metal at the bottom surface of said basin and for maintaining the divider plate in position in said sink.Type: GrantFiled: February 28, 2013Date of Patent: January 28, 2014Inventors: Vincent A. Giagni, Sr., John D. Hyde
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Patent number: 8600298Abstract: RFID tags, tag circuits, and methods are provided that reject at least in part the distortion caused to wireless signals by interference in the environment. When the received RF wave is converted into an unfiltered input (971), a filtered output (972) is generated that does not include an artifact feature deriving from the distortion. The filtered output is used instead of the unfiltered input, which results in tag operation as if there were less interference in the environment, or none at all.Type: GrantFiled: November 1, 2012Date of Patent: December 3, 2013Assignee: Impinj, Inc.Inventors: John D. Hyde, Kurt E. Sundstrom
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Patent number: 8416630Abstract: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.Type: GrantFiled: January 3, 2012Date of Patent: April 9, 2013Assignee: Synopsys, Inc.Inventors: Alberto Pesavento, John D. Hyde
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Patent number: 8391785Abstract: RFID tags, tag circuits, and methods are provided that reject at least in part the distortion caused to wireless signals by interference in the environment. When the received RF wave is converted into an unfiltered input (971), a filtered output (972) is generated that does not include an artifact feature deriving from the distortion. The filtered output is used instead of the unfiltered input, which results in tag operation as if there were less interference in the environment, or none at all.Type: GrantFiled: March 30, 2010Date of Patent: March 5, 2013Assignee: Impinj, Inc.Inventors: John D. Hyde, Kurt E. Sundstrom
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Patent number: 8344857Abstract: The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The rectifier is constructed from a pair of complementary MOS transistors. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating region. During the same time additional control signals are applied to the gates of the transistors, the control signals are synchronous, but out of phase, with each other.Type: GrantFiled: November 30, 2011Date of Patent: January 1, 2013Assignee: Impinj, Inc.Inventors: Ronald A. Oliver, John D. Hyde, Charles J. T. Peach
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Patent number: 8325042Abstract: An Integrated Circuit (IC) for an RFID tag contains at least two demodulators, each having an RF input port configured to receive and demodulate an RF input signal, with one or more of the RF inputs being a differential signal, and with at least two of the RF input ports electrically isolated from each other. The RFID IC contains two or more envelope detectors for recovering analog modulation envelope signals from the RF signals, and one or more slicers to convert the modulation envelopes to at least one digital signal. The analog signals from the two envelope detectors may be first combined, then converted to a digital signal. Alternatively, the analog modulation envelopes may be first converted to digital signals then combined in a digital combiner. Alternatively, the analog modulation envelopes may be converted to separate digital signals without being combined.Type: GrantFiled: February 12, 2010Date of Patent: December 4, 2012Assignee: Impinj, Inc.Inventors: John D. Hyde, Ronald A. Oliver, Christopher J. Diorio
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Patent number: 8258955Abstract: RFID tags, tag circuits, and methods are provided that reduce at least in part the distortion to received wireless signals, which is caused by interference in the environment. Two or more thresholds are used to digitize the received signal implemented by two or more demodulators. Multiple low pass and digital filters may be implemented with the demodulators, allowing removal of narrow pulses caused by the interference and reduction of beat tone amplitude.Type: GrantFiled: January 24, 2011Date of Patent: September 4, 2012Assignee: Impinj, Inc.Inventors: John D. Hyde, Kurt E. Sundstrom
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Patent number: 8260241Abstract: RFID readers configured to transmit a radio frequency signal include a sub-orthogonal self-jammer cancellation circuit that generates two or more distinct phase variants of the transmit signal, selects two of the phase variants with a vector projection of one of the selected phase variants on another of the selected phase variants being substantially greater than zero such that a canceling signal comprising a combination of the at least two phase variants is substantially opposite in phase to a self-jamming signal, and selects amplitudes for the at least two selected phase variants such that the canceling signal is substantially equal in amplitude to the self-jamming signal. The canceling signal is then combined with the self-jamming signal to reduce the amplitude of an RF signal received by a receive circuit.Type: GrantFiled: October 28, 2010Date of Patent: September 4, 2012Assignee: Impinj, Inc.Inventor: John D. Hyde
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Patent number: 8193912Abstract: RFID tags are configured to adjust their clock frequency in order to meet predefined limits for reply frequencies to conserve tag power. A deviation of computed tag reply frequency from a reader commanded reply frequency is used to determine an adjustment to the tag clock frequency. The tag clock frequency may be adjusted during backscatter and restored once backscattering is completed.Type: GrantFiled: March 12, 2009Date of Patent: June 5, 2012Assignee: Impinj, Inc.Inventors: Vadim Gutnik, Scott A. Cooper, John D. Hyde
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Publication number: 20120099380Abstract: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.Type: ApplicationFiled: January 3, 2012Publication date: April 26, 2012Applicant: SYNOPSYS, INC.Inventors: Alberto Pesavento, John D. Hyde
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Patent number: 8115597Abstract: The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The rectifier is constructed from a pair of complementary MOS transistors. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating region. During the same time additional control signals are applied to the gates of the transistors, the control signals are synchronous, but out of phase, with each other.Type: GrantFiled: March 4, 2008Date of Patent: February 14, 2012Assignee: Impinj, Inc.Inventors: Ronald A. Oliver, John D. Hyde, Charles J. T. Peach
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Patent number: 8111558Abstract: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.Type: GrantFiled: October 2, 2007Date of Patent: February 7, 2012Assignee: Synopsys, Inc.Inventors: Alberto Pesavento, John D. Hyde
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Patent number: 8102007Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.Type: GrantFiled: September 12, 2003Date of Patent: January 24, 2012Assignee: Synopsys, Inc.Inventors: John D. Hyde, Miguel E. Figueroa, Todd E. Humes, Christopher J. Diorio, Terry D. Hass, Chad A. Lindhorst
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Patent number: 8076707Abstract: A semiconductor device is provided that uses a floating gate to store analog- and digital-valued information for periods of time measured in milliseconds to hours. Charge is added to and/or removed from the floating gate by means of direct electron tunneling through the surrounding insulator, with the insulator typically being thin enough such that appreciable tunneling occurs with an insulator voltage smaller than the difference in electron affinities between the semiconductor and the insulator and/or between the floating gate and the insulator. The stored information is refreshed or updated as needed. In many applications, the stored information can be refreshed without interrupting normal circuit operation. Adding and removing charge to or from the floating gate may be performed using separate circuit inputs, to tailor the performance and response of the floating-gate device. There is no need to use a control gate in the floating-gate structures disclosed herein.Type: GrantFiled: September 12, 2005Date of Patent: December 13, 2011Assignee: Synopsys, Inc.Inventors: John D. Hyde, Todd E. Humes, Christopher J. Diorio, Carver A. Mead
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Patent number: 8044801Abstract: The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The power rectifier is constructed from a pair of complementary MOS transistors. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating regions, while an additional RF control signal is being applied to only one of the gates of the transistors in the complementary pair.Type: GrantFiled: March 4, 2008Date of Patent: October 25, 2011Assignee: Impinj, Inc.Inventors: John D. Hyde, Ronald A. Oliver, Charles J. T. Peach
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Patent number: 7990249Abstract: RFID tag circuits, tags, and methods are provided for backscattering a received RF wave using a controllable admittance difference between the ON state and the OFF state. The admittance difference is controlled responsive to a control signal. In some embodiments, the control signal is generated responsive to a command. In others, the control signal is generated responsive to detecting the power level of the received RF wave. In those, the inherent behavior of the admittance difference can be shaped as desired. For example, it can be such that the backscatters with advantageously more power when it is away from the reader, and with less power when it is close to the reader, so as to meet regulatory requirements.Type: GrantFiled: June 20, 2007Date of Patent: August 2, 2011Assignee: Impinj, Inc.Inventors: John D. Hyde, Ronald A. Oliver
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Patent number: 7978005Abstract: Embodiments of the invention describe a core circuit for a reference current generator circuit that biases a first transistor to source a first current and a second transistor parallel to the first transistor, biased to source a second current controlled by the first current. A third transistor is coupled parallel to the second transistor and sources a third current controlled by the first current. The third transistor has a different threshold voltage than a threshold voltage of the second transistor. A resistive component coupled to conduct the second current has a resistive voltage that is substantially equal to a voltage differential between the first transistor and the second transistor. The conducting current through the resistive component is substantially independent of temperature variations.Type: GrantFiled: May 23, 2009Date of Patent: July 12, 2011Assignee: Impinj, Inc.Inventors: John D. Hyde, Christopher J. Diorio