Patents by Inventor John D. Hyde

John D. Hyde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7973643
    Abstract: RFID readers transmit data to query tags at one or more data rates. Before transmitting data, the RFID readers also transmit special preambles that inform of the data rate that will be used for transmitting the data. The preambles have a call aspect and a rate aspect. The rate aspect has a feature substantially determined from a rate selected for transmitting the data. The feature may encode the rate indirectly or explicitly. The call aspect may be implemented by call transitions that define a timing, whose duration is independent of the selected rate. The duration may be advantageously set according to an assumed state of the RFID tag bandwidth filter. Therefore an RFID tag may use the call aspect of the preamble to prepare itself for receiving data, and the rate aspect to determine its rate of transmission for setting its filter bandwidth accordingly.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: July 5, 2011
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Christopher J. Diorio
  • Patent number: 7969236
    Abstract: Embodiments of the invention describe a core circuit for a reference current generator circuit that biases a first transistor to source a first current and a second transistor parallel to the first transistor, biased to source a second current controlled by the first current. A third transistor is coupled parallel to the second transistor and sources a third current controlled by the first current. The third transistor has a different threshold voltage than a threshold voltage of the second transistor. A resistive component coupled to conduct the second current has a resistive voltage that is substantially equal to a voltage differential between the first transistor and the second transistor. The conducting current through the resistive component is substantially independent of temperature variations.
    Type: Grant
    Filed: May 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Christopher J. Diorio
  • Patent number: 7917088
    Abstract: RFID tags, tag circuits, and methods are provided that reduce at least in part the distortion to received wireless signals, which is caused by interference in the environment. Two or more thresholds are used to digitize the received signal implemented by two or more demodulators. Multiple low pass and digital filters may be implemented with the demodulators, allowing removal of narrow pulses caused by the interference and reduction of beat tone amplitude.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: March 29, 2011
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Kurt E. Sundstrom
  • Patent number: 7861390
    Abstract: European-style long rail pulls are installed on cabinet doors to replace previously installed knobs or short handles on such cabinet doors. Standoff devices are used to rigidly secure the European-style rail pulls while covering unsightly holes left exposed after removal of the knobs from the cabinet doors. The standoff device is a generally cylindrical body have a flat bottom surface and a bore aligned with the exposed holes on the cabinet doors, and an upper surface shaped and sized to securely grip the long rail about its circumference.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: January 4, 2011
    Inventors: Vincent Giagni, John D. Hyde
  • Patent number: 7768248
    Abstract: Embodiments of the invention describe a reference current generator circuit having a core circuit that includes a first transistor in a first current path for conduct a first current and a second transistor in a second current path for conduct a second current. The second transistor has a threshold voltage that is different from the threshold voltage of the first transistor by at least 10%. The voltage differential between the first and second transistors generate a voltage across a resistive component coupled in series with the second transistor in the second current path.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 3, 2010
    Assignee: Impinj, Inc.
    Inventor: John D. Hyde
  • Patent number: 7768406
    Abstract: The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The power rectifier can be constructed from serially coupled rectifier stages. One of the rectifier stages includes a backflow reduction device or a bias preservation circuit, or both, at least one of which us controlled by a signal derived from a control signal source of the tag circuit.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: August 3, 2010
    Assignee: Impinj, Inc.
    Inventors: Charles J. T. Peach, John D. Hyde
  • Publication number: 20100182129
    Abstract: RFID tags, tag circuits, and methods are provided that reject at least in part the distortion caused to wireless signals by interference in the environment. When the received RF wave is converted into an unfiltered input (971), a filtered output (972) is generated that does not include an artifact feature deriving from the distortion. The filtered output is used instead of the unfiltered input, which results in tag operation as if there were less interference in the environment, or none at all.
    Type: Application
    Filed: March 30, 2010
    Publication date: July 22, 2010
    Applicant: Impinj, Inc.
    Inventors: John D. Hyde, Kurt E. Sundstrom
  • Patent number: 7733227
    Abstract: Feasibility of a requested action by a reader is predetermined in an RFID tag based on an available tag power level. A pretest that is designed to consume artificially high levels of power is performed and the power level monitored to determine if a preset condition is met. The pretest may include activation of selected components such as a memory and associated support circuitry. If the preset condition is not met, the requested action is aborted and an error message transmitted to the reader.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: June 8, 2010
    Assignee: Impinj, Inc.
    Inventors: Alberto Pesavento, Vadim Gutnik, John D. Hyde
  • Patent number: 7715236
    Abstract: Methods and structure for fault tolerant Non Volatile Memory (NVM) devices are provided. Readings of selected memory cells are compared to two thresholds above and below a neutral value. Consistency of comparison outputs is used to determine a good or bad reading. Parity bit correction can be used to correct bad readings.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: May 11, 2010
    Assignee: Virage Logic Corporation
    Inventor: John D. Hyde
  • Patent number: 7667231
    Abstract: Microcircuits may include polysilicon features that are vulnerable to defects due to undesirable phenomena during manufacturing processes such as, inter alia, over-etching. The same phenomena that may cause defects can be exploited to automatically isolate the affected circuit and thus limit the harm caused by defects or incipient defects.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: February 23, 2010
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Jay A. Kuhn, Ronald L. Koepp, Ronald E. Paulsen
  • Patent number: 7541843
    Abstract: A radio frequency identification (RFID) circuit including a semi-static flip-flop having a static storage time longer than its dynamic storage time. The RFID circuit may include a timing block circuit to provide a timing block clock signal to the semi-static flip-flop, the signal having a first clock state duration shorter than the dynamic storage time and a second clock state duration longer than the dynamic storage time.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: June 2, 2009
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Dennis Kiyoshi Hara, David D. Dressler
  • Patent number: 7525438
    Abstract: Circuits, devices and methods for use in RFID tags include receiving multiple RF signals from multiple ports. The signals are added after some processing, to produce a single combined signal. Additional components process the single combined signal by itself.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: April 28, 2009
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Omer Onen, Ronald A. Oliver
  • Publication number: 20080258594
    Abstract: European-style long rail pulls are installed on cabinet doors to replace previously installed knobs or short handles on such cabinet doors. Standoff devices are used to rigidly secure the European-style rail pulls while covering unsightly holes left exposed after removal of the knobs from the cabinet doors. The standoff device is a generally cylindrical body have a flat bottom surface and a bore aligned with the exposed holes on the cabinet doors, and an upper surface shaped and sized to securely grip the long rail about its circumference.
    Type: Application
    Filed: April 23, 2007
    Publication date: October 23, 2008
    Inventors: Vincent Giagni, John D. Hyde
  • Patent number: 7423539
    Abstract: Circuits, devices and methods for use in RFID tags include receiving multiple RF signals from multiple ports. The signals are added after some processing, to produce a single combined signal. Additional components process the single combined signal by itself.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: September 9, 2008
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Omer Onen, Ronald A. Oliver
  • Patent number: 7405659
    Abstract: An RFID tag that receives an RF signal from a reader is arranged to derive a threshold signal from a detected envelope of the RF signal, where the threshold signal is proportional to the detected envelope signal. The detected envelope signal is then compared to the threshold signal to derive a digital signal from the received RF signal. By maintaining the threshold signal proportional to the detected envelope signal, false bit detections due to ripple effect on the received signal and interference from other sources are reduced. The threshold signal may be derived employing a switched capacitor attenuator circuit.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: July 29, 2008
    Assignee: Impinj, Inc.
    Inventor: John D. Hyde
  • Publication number: 20080175050
    Abstract: A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.
    Type: Application
    Filed: October 2, 2007
    Publication date: July 24, 2008
    Inventors: ALBERTO PESAVENTO, John D. Hyde
  • Patent number: 7312622
    Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: December 25, 2007
    Assignee: Impinj, Inc.
    Inventors: John D. Hyde, Robert M. Glidden, Andrew Edward Horch, Jay A. Kuhn, Ronald A. Oliver
  • Patent number: 7307528
    Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: December 11, 2007
    Assignee: IMPINJ, Inc.
    Inventors: Robert M. Glidden, Dennis Kiyoshi Hara, Ronald A. Oliver, Jay A. Kuhn, John D. Hyde
  • Patent number: 7307529
    Abstract: An RFID tag has a fuse that is adapted to store configuration data in a way that survives loss of power. The fuse can be one time programmable or many times programmable, and be implemented with a non-volatile memory. The configuration data becomes available to an operational component of the tag, such as at power up, controlling its performance.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: December 11, 2007
    Assignee: IMPINJ, Inc.
    Inventors: Vadim Gutnik, John D. Hyde, David D. Dressler, Alberto Pesavento, Ronald A. Oliver, Scott Anthony Cooper, Kurt Eugene Sundstrom
  • Patent number: 7221596
    Abstract: A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/information storage. A control capacitor structure (CCS) having terminals coupled to a first voltage source and the FG and a tunneling capacitor structure (TCS) having terminals coupled to a second voltage source and the FG are utilized in each embodiment. The CCS has much more capacitance than the TCS. Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the CCS and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the FG, thus controlling the charge on the FG and the information stored thereon.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: May 22, 2007
    Assignee: Impinj, Inc.
    Inventors: Alberto Pesavento, Frédéric J. Bernard, John D. Hyde