Abstract: A Radio-Frequency Identification (RFID) transponder is provided. The RFID transponder may include a basic ID flag circuit having a VDD voltage node, an output voltage node, and a capacitor coupled to the VDD voltage node and the output voltage node to store an ID flag. A supplemental discharge current circuit coupled to the basic ID flag circuit is provided in order to control persistence duration of the state of the ID flag. The persistence duration of the state of the ID flag is controlled by maintaining supplemental discharge current, which is greater than the leakage current of the basic ID flag circuit.

Abstract: RFID readers exchange information with RFID tags. The information is encoded for transmission and decoded upon reception. Encoding is in binary bits, which are in turn encoded in waveform segments. The last transmitted waveform incorporates an ending-triggering transition, and terminates in a preset manner with respect to when the ending-triggering transition occurs. Parsing while decoding can happen by waiting for the ending-triggering transition, and then waiting according to the preset manner. This way there is no ambiguity in the ending of the waveform, and no End Frame is necessary.

Abstract: RFID tags, tag circuits, and methods adapting the reception bandwidth. A tag has a decoder for decoding a first received wireless signal subject to a reception bandwidth setting. The tag also has a selector switch for transitioning to a different setting, such as by switching to using a different filter. A subsequently received second signal is decoded subject to the new reception bandwidth setting.

Abstract: Circuits are provided for high-voltage switching in single-well CMOS processes.

Abstract: A Radio-Frequency Identification (RFID) transponder is provided. The RFID transponder may include a basic ID flag circuit having a VDD voltage node, an output voltage node, and a capacitor coupled to the VDD voltage node and the output voltage node to store an ID flag. The persistence duration of the state of the ID flag is controlled by maintaining a charge and leakage circuit. The charge and leakage circuit includes an NMOS device having a source, a drain and a gate, the source node of the NMOS device being coupled to the capacitor and the drain node of the NMOS device being coupled to a first CMOS inverter. The first CMOS inverter is powered by a regulated supply voltage such that the voltage on the capacitor is not dependent on the forward voltage drop of the NMOS device.

Abstract: RFID readers exchange information with RFID tags. The information is encoded for transmission and decoded upon reception. Encoding is in binary bits, which are in turn encoded in waveform segments. The last transmitted waveform incorporates an ending-triggering transition, and terminates in a preset manner with respect to when the ending-triggering transition occurs. Parsing while decoding can happen by waiting for the ending-triggering transition, and then waiting according to the preset manner. This way there is no ambiguity in the ending of the waveform, and no End Frame is necessary.

Abstract: Methods and apparatus provide for front-end processing of a first differential output current, whereby a first differential output current is received and a second differential output current having reduced spurious content is produced. Current steering is used to divide, and reassemble, the first differential output current so as to provide an output signal with reduced spurious content. Current steering is implemented by a return-to-zero circuit that is coupled to the terminals of a first differential current output stage. During a first phase, the return-to-zero circuit provides a differential output current equal to the first differential current output. During a second phase, the return-to-zero circuit provides a differential output current equal to zero. The current steering return-to-zero circuit is implemented with MOSFETs or any other suitable electrical circuit element that provides the ability to controllably pass or refrain from passing current.

Abstract: A method and apparatus for calibrating an electronic circuit which required scaled matching of some or all of its electronic components with nonvolatile programmably trimmable parameter sources (current, voltage, resistance, capacitance) is carried out in a top-down (highest order bit first, lowest order bit last) fashion without an analog division step. The method and apparatus are applicable, for example, to current-steering digital-to-analog converters (DACs), voltage-controlled oscillators (VCOs), voltage-steering DACs, and the like. In each of these applications the method and apparatus is used to match successive device outputs according to a desired scale factor, proceeding top-down from large output devices to smaller output devices, thereby successively shrinking the cross-device errors which accrue during the matching process.

Abstract: A simple metal dielectric semiconductor (MDS) variable capacitor which may be a MOS capacitor uses the drain and source of a floating gate metal dielectric semiconductor field effect transistor connected to the bulk of the semiconductor substrate as one plate of the capacitor and the gate of the transistor as the other plate. The capacitance is voltage dependent and is strongly nonlinear in the depletion region. The accumulation and strong inversion regions are also nonlinear, but to a much smaller degree. The nonlinearity can be significantly reduced by connecting two of the capacitors in series. This series connection also makes possible a capacitor structure with an isolated floating gate connecting the two series capacitors. The charge on the floating gate can be controlled by tunneling and injection to vary the capacitor bias voltage and thus, its capacitance. Alternatively, the capacitors may operate in the accumulation region.

Abstract: A semiconductor device is provided that uses a floating gate to store analog- and digital-valued information for periods of time measured in milliseconds to hours. Charge is added to and/or removed from the floating gate by means of direct electron tunneling through the surrounding insulator, with the insulator typically being thin enough such that appreciable tunneling occurs with an insulator voltage smaller than the difference in electron affinities between the semiconductor and the insulator and/or between the floating gate and the insulator. The stored information is refreshed or updated as needed. In many applications, the stored information can be refreshed without interrupting normal circuit operation. Adding and removing charge to or from the floating gate may be performed using separate circuit inputs, to tailor the performance and response of the floating-gate device. There is no need to use a control gate in the floating-gate structures disclosed herein.

Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.

Abstract: A high speed differential optoelectronic receiver comprises a first photodetector responsive to a first incident amplitude modulated optical signal and operative to develop a first electrical signal, a second photodetector responsive to a second incident amplitude modulated optical signal that is complementary to the first optical signal and operative to develop a second electrical signal, and an amplifier having a first input that is responsive to the first electrical signal and a second input that is responsive to the second electrical signal and is operative to provide a differential output signal that is proportional to the difference between the first and the second electrical signals. Also, a method for transforming complementary amplitude modulated optical signals into a complementary electrical output signal is invented.