Patents by Inventor John David Baniecki
John David Baniecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7937830Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: GrantFiled: June 18, 2008Date of Patent: May 10, 2011Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
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Patent number: 7927998Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.Type: GrantFiled: January 8, 2010Date of Patent: April 19, 2011Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
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Publication number: 20110073993Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: FUJITSU LIMITEDInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7867869Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.Type: GrantFiled: June 11, 2003Date of Patent: January 11, 2011Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7832069Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed on a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).Type: GrantFiled: April 27, 2007Date of Patent: November 16, 2010Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Publication number: 20100233796Abstract: A fuel cell system includes a fuel cell configured to generate electric power with a fuel gas and an oxygen gas fed to the fuel cell and to discharge exhaust gas including CO2 as a result of generating the electric power; a CO extraction part configured to reduce the CO2 in the exhaust gas fed to the CO extraction part to CO, the CO extraction part including a processing container fed with the exhaust gas and a CO2 adsorbing member provided in the processing container and formed of an oxide having an oxygen deficiency; and a CO recycling part configured to feed the extracted CO to the fuel cell as part of the fuel gas.Type: ApplicationFiled: March 9, 2010Publication date: September 16, 2010Applicant: FUJITSU LIMITEDInventors: Kazuaki KURIHARA, John David Baniecki, Masatoshi Ishii
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Publication number: 20100112775Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.Type: ApplicationFiled: January 8, 2010Publication date: May 6, 2010Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
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Patent number: 7670940Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.Type: GrantFiled: October 17, 2005Date of Patent: March 2, 2010Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
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Patent number: 7618859Abstract: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.1<R<0.2.Type: GrantFiled: July 24, 2008Date of Patent: November 17, 2009Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7614142Abstract: A method for fabricating an interposer includes: forming on one primary surface of a first substrate a thin-film capacitor including a first capacitor electrode, a crystalline capacitor dielectric film formed on the first electrode and a second capacitor electrode formed on the dielectric film; and forming on the primary surface of the first substrate and the capacitor a first layer as semi-cured, and a first partial electrode to be a part of a through-electrode, buried in the first resin layer and electrically connected to the first electrode or the second electrode.Type: GrantFiled: February 5, 2008Date of Patent: November 10, 2009Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
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Patent number: 7587229Abstract: A superconducting tunable filter comprises a dielectric base plate; a patch-shaped resonator pattern formed of a superconducting material on the dielectric base plate; a top dielectric locally placed on the superconducting resonator pattern at a prescribed position and made of a material with an electric-field dependent permittivity; a conducting pattern formed on a top face of the top dielectric; and a bias voltage supply configured to apply a bias voltage between the conducting pattern and the superconducting resonator pattern.Type: GrantFiled: March 27, 2007Date of Patent: September 8, 2009Assignee: Fujitsu LimitedInventors: Masatoshi Ishii, Kazunori Yamanaka, Akihiko Akasegawa, John David Baniecki, Kazuaki Kurihara, Teru Nakanishi
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Patent number: 7491996Abstract: A capacitive element includes a base member 10, an underlying insulating film 11 formed on the base member 10, a capacitor Q constructed by forming a lower electrode 13, a capacitor dielectric film 14, and an upper electrode 15 sequentially on the underlying insulating film 11, a lower protection insulating film 16a formed on the upper electrode 15 to cover at least a part of the capacitor Q, and an upper protection insulating film 16b formed on the lower protection insulating film 16a and having a wider energy band gap than the lower protection insulating film 16a.Type: GrantFiled: June 29, 2005Date of Patent: February 17, 2009Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Publication number: 20090007405Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed on a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).Type: ApplicationFiled: April 27, 2007Publication date: January 8, 2009Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Patent number: 7473949Abstract: After a step of fabricating a MOS transistor (14) on a semiconductor substrate (11) and further steps up to bury a W plug (24), an Ir film (25a), an IrOy film (25b), a PZT film (26), and an IrOx film (27) are formed sequentially over the entire surface. The composition of the PZT film (26) is such that the content of Pb exceeds that of Zr and that of Ti. After processing the Ir film (25a), the IrOy film (25b), the PZT film (26) and the IrOx film (27), annealing is effected to remedy the damage to the PZT film (26) that is caused when the IrOx film (27) is formed and to diffuse Ir in the IrOx film (27) into the PZT film (26). As a result, the Ir diffused into the PZT film (26) concentrates at an interface between the IrOx film (27) and the PZT film (26) and at grain boundaries in the PZT film (26), and the Ir concentrations at the interface and boundaries are higher than those in the grains.Type: GrantFiled: March 17, 2005Date of Patent: January 6, 2009Assignee: Fujitsu LimitedInventors: Jeffrey Scott Cross, Mineharu Tsukada, John David Baniecki, Kenji Nomura, Igor Stolichnov
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Publication number: 20080315358Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).Type: ApplicationFiled: August 15, 2008Publication date: December 25, 2008Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Patent number: 7466152Abstract: A probe card including probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.Type: GrantFiled: July 14, 2006Date of Patent: December 16, 2008Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Publication number: 20080305607Abstract: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.1<R<0.2.Type: ApplicationFiled: July 24, 2008Publication date: December 11, 2008Applicant: FUJITSU LIMITEDInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7456078Abstract: The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor electrode 18 formed over the capacitor dielectric film 16; leading-out electrodes 26a, 26b lead from the first capacitor electrode 14 or the second capacitor electrode 18 and formed of a conducting barrier film which prevents the diffusion of hydrogen or water; and outside connection electrodes 34a, 34b for connecting to outside and connected to the leading-out electrodes 26a, 26b.Type: GrantFiled: March 31, 2006Date of Patent: November 25, 2008Assignee: Fujitsu LimitedInventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki, Masatoshi Ishii
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Publication number: 20080257487Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: ApplicationFiled: June 18, 2008Publication date: October 23, 2008Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
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Patent number: 7439199Abstract: A capacitive element is characterized by including: a base (12); a lower barrier layer (13) formed on the base (12); capacitors (Q1 and Q2) made by forming a lower electrode (14a), capacitor dielectric layers (15a), and upper electrodes (16a) in this order on the lower barrier layer (13); and an upper barrier layer (20) covering at least the capacitor dielectric layers (15a) and the lower barrier layer (13).Type: GrantFiled: October 17, 2006Date of Patent: October 21, 2008Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara