Patents by Inventor John David Baniecki
John David Baniecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080242550Abstract: The tunable filter includes two or more adjacent resonators, and a variable capacitive coupler formed on the same substrate where the resonators are formed provided between the resonators. The tunable filter is appropriate for integration which can efficiently change a coupling capacitance between the resonators using a simple structure.Type: ApplicationFiled: March 25, 2008Publication date: October 2, 2008Applicant: FUJITSU LIMITEDInventors: Masatoshi ISHII, Kazunori YAMANAKA, John David BANIECKI, Akihiko AKASEGAWA
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Patent number: 7417276Abstract: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.1<R<0.2.Type: GrantFiled: October 18, 2006Date of Patent: August 26, 2008Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7405366Abstract: An interposer 2 including a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further including: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.Type: GrantFiled: January 26, 2006Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, John David Baniecki, Kazuaki Kurihara
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Patent number: 7405921Abstract: In one aspect of the invention, a thin layer capacitor element has a capacitor with a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, and a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.Type: GrantFiled: July 14, 2006Date of Patent: July 29, 2008Assignee: Fujitsu LimitedInventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki, Mamoru Kurashina
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Publication number: 20080134499Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.Type: ApplicationFiled: February 5, 2008Publication date: June 12, 2008Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
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Patent number: 7365327Abstract: An SiO2 layer (3), a Ti layer (4), a Pt layer (5), a PLZT layer (6) and an IrO2 layer (7) are formed sequentially on an Si substrate (2). The IrO2 layer (7) functioning as a top electrode has a thickness of about 100 nm. Since the IrO2 layer (7) has conductivity lower than that of Pt or the like conventionally used as a top electrode and a skin depth deeper than that of Pt or the like, sufficient sensitivity can be attained by a thickness of about 100 nm.Type: GrantFiled: March 23, 2005Date of Patent: April 29, 2008Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7355290Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.Type: GrantFiled: January 25, 2006Date of Patent: April 8, 2008Assignee: Fujitsu LimitedInventors: Takeshi Shioga, Yoshikatsu Ishizuki, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi, John David Baniecki, Kazuaki Kurihara
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Patent number: 7349195Abstract: The present invention provides the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.Type: GrantFiled: October 16, 2006Date of Patent: March 25, 2008Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurhara
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Patent number: 7326989Abstract: A thin film capacitor is provided which includes a single crystal high dielectric constant dielectric layer. The thin film capacitor has a single crystal silicon substrate, a single crystal intermediate layer epitaxially grown on the single crystal silicon substrate, a single crystal lower electrode epitaxially grown on the single crystal intermediate layer, a single crystal high dielectric constant dielectric layer epitaxially grown on the lower electrode layer, an upper electrode layer formed above the single crystal high dielectric constant dielectric layer, and a plurality of conductor terminals connected to the lower electrode layer and upper electrode layer at a plurality of positions.Type: GrantFiled: February 28, 2005Date of Patent: February 5, 2008Assignee: FUJITSU LimitedInventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki
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Publication number: 20070232017Abstract: A thin film capacitor comprising a top electrode, a bottom electrode, and a dielectric film held between the top and bottom electrodes. The dielectric film is composed of at least cations Ba, Sr, and Ti and anion O. The concentration of Sr, Ti, and O ions are uniform along the growth direction of the dielectric film while the concentration of the Ba cation is non-uniform along the growth direction such that a reduced Ba-I region in which the average concentration of perovskite type Ba cations (Ba-I) is less than the average concentration of non-perovskite type Ba cations (Ba-II) exists at or near the boundary between at least one of the top and bottom electrodes, with ratio R=(atm % Ba-I)/[(atm % Ba-I)+(atm % Ba-II)] within a range of 0.1<R<0.2.Type: ApplicationFiled: October 18, 2006Publication date: October 4, 2007Applicant: FUJITSU LIMITEDInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7251117Abstract: A semiconductor device having the thin film capacitor includes a first electrode formed on a substrate, a capacitor insulating film containing a laminated film, which is constructed by laminating an amorphous dielectric film and a polycrystalline dielectric film via a wave-like interface, on the first electrode, and a second electrode formed on the capacitor insulating film.Type: GrantFiled: September 15, 2004Date of Patent: July 31, 2007Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7227736Abstract: A capacitor device includes a capacitor Q constituted by a lower electrode (12) formed an a substrate (10), a dielectric film (14), and an upper electrode (16); an insulating film (18) covering the capacitor Q; a first contact hole (18a) formed in the insulating film (18) on a connection portion (16a) of the upper electrode (16); an electrode pad (20) for preventing a diffusion of solder, formed in the first contact hole (18a); and a solder bump (22) electrically connected to the electrode pad (20), and the upper electrode (16) has a protrusion portion (16a) protruding from the dielectric film (14), and is connected to the first contact hole (18a) on the protrusion portion (16a).Type: GrantFiled: February 15, 2005Date of Patent: June 5, 2007Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Patent number: 7180119Abstract: The capacitor according to the present invention comprises a lower electrode 18 formed on a base substrate 14, a dielectric film 20 formed on the lower electrode 18, and an upper electrode 28 formed on the dielectric film 20 and including a polycrystalline conduction film 22, and a amorphous conduction film 24 formed on the polycrystalline conduction film 22. Because of the amorphous conduction film 24 included in the upper electrode 28, which can shut off hydrogen and water, hydrogen and water can be prohibited from arriving at the dielectric film 20. Accordingly, the dielectric film 20 of an oxide is prevented from being reduced with hydrogen, and the capacitor can have good electric characteristics.Type: GrantFiled: May 21, 2004Date of Patent: February 20, 2007Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7172945Abstract: A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.Type: GrantFiled: October 28, 2004Date of Patent: February 6, 2007Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Patent number: 7161793Abstract: In one aspect of the invention, in a thin layer capacitor element comprising a capacitor having a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.Type: GrantFiled: November 13, 2003Date of Patent: January 9, 2007Assignee: Fujitsu LimitedInventors: Kazuaki Kurihara, Takeshi Shioga, John David Baniecki, Mamoru Kurashina
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Patent number: 7161200Abstract: A capacitive element which includes: a silicon substrate (base material) 1; a base insulating film 2 formed on the silicon substrate 1; and a capacitor Q constituted by forming a bottom electrode 4a, a capacitor dielectric film 5a and a top electrode 6a on the base insulating film 2. The capacitive element is characterized in that the capacitor dielectric film 5a is composed of a material with the formula (Ba1?y,Sry)mYpTiQO3+?, where 0<p/(p+m+Q)?0.015, ?0.5<?<0.5.Type: GrantFiled: December 20, 2004Date of Patent: January 9, 2007Assignee: Fujitsu LimitedInventors: John David Baniecki, Kenji Nomura, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 7102367Abstract: A probe card includes probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.Type: GrantFiled: July 18, 2003Date of Patent: September 5, 2006Assignee: Fujitsu LimitedInventors: Yasuo Yamagishi, Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Patent number: 7026680Abstract: An integrated thin film capacitive element comprising a dielectric material of the specified composition that exhibits increased voltage tunability of capacitance and capacitance density and a production process thereof are disclosed. The integrated thin film capacitive element comprises a capacitor structure constituted from a lower electrode, a dielectric layer comprised of the high dielectric constant material represented by the formula: (Ba(1-y)(1-x)Sr(1-y)xYy)Ti1+zO3+? with the range 0<x<1, 0.007<y<0.02, ?1<?<0.5, and (Ba(1-y)(1-x)+Sr(1-y)x)/Ti1+z<1, and an upper electrode. An electronic device comprising the capacitive element of the present invention is also disclosed.Type: GrantFiled: March 3, 2004Date of Patent: April 11, 2006Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 6975501Abstract: An electronic device comprises a silicon substrate (base material), an underlying insulating film formed on the silicon substrate, a capacitor constructed by forming a bottom electrode, a capacitor dielectric film, and a top electrode sequentially on the underlying insulating film, and a voltage supply circuit for supplying a voltage with a bipolar waveform to at least one of the bottom electrode and the top electrode, wherein an amplitude of the voltage is set to 5×105 d (V) or less (d: an interval (cm) between the top electrode and the bottom electrode). Accordingly, an electronic device and a method of applying a voltage to a capacitor, capable of prolonging a lifetime of a capacitor by preventing degradation of a capacitor dielectric film are provided.Type: GrantFiled: December 16, 2004Date of Patent: December 13, 2005Assignee: Fujitsu LimitedInventors: John David Baniecki, Takeshi Shioga, Kazuaki Kurihara
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Patent number: 6894396Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.Type: GrantFiled: July 16, 2003Date of Patent: May 17, 2005Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara, Yasuo Yamagishi