Abstract: A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function.

Abstract: A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected.

Abstract: A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.

Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.

Abstract: A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.

Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Abstract: A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.

Abstract: A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back end of the line (BEOL) portion of the semiconductor chip. The FETs are used to make buffer circuits in the BEOL to improve delay and signal integrity of long signal paths on the semiconductor chip.

Abstract: A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

Abstract: Vertically stacked Field Effect Transistors (FETs) are created on a vertical structure formed on a semiconductor substrate where a first FET and a second FET are controllable independently. A bipolar junction transistor is connected between and in series with the first FET and the second FET, the bipolar junction transistor may be controllable independently of the first and second FET.

Abstract: In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line is driven to a high voltage state. The word line is driven to a predetermined voltage state that causes bias temperature instability in the FET. The temperature, the high voltage state on the bit line and the predetermined voltage state on the word line are maintained for an amount of time sufficient to change a threshold voltage of the FET to a state where a desired data value is stored on the FET. The FET is cooled to a second temperature that is cooler than the first temperature after the amount of time has expired.

Abstract: The present invention provides a method and apparatus for measuring alignment, rotation and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation.

Abstract: A vertical structure is formed upon a semiconductor substrate. The vertical structure comprises four dielectric layers parallel to a top surface of the semiconductor substrate and three conducting layers, one conducting layer between each vertically adjacent dielectric layer. A first FET (field effect transistor) and a third FET are arranged parallel to the top surface of the semiconductor and a second FET is arranged orthogonal to the top surface of the semiconductor. All three FETs are independently controllable. The first conducting layer is a gate electrode of the first FET; the second conducting layer is a gate electrode of the second FET, and the third conducting layer is the gate electrode of the third FET.

Abstract: A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are b

Abstract: A processor-implemented method for determining aging of a processing unit in a processor the method comprising: calculating an effective aging profile for the processing unit wherein the effective aging profile quantifies the effects of aging on the processing unit; combining the effective aging profile with process variation data, actual workload data and operating conditions data for the processing unit; and determining aging through an aging sensor of the processing unit using the effective aging profile, the process variation data, the actual workload data, architectural characteristics and redundancy data, and the operating conditions data for the processing unit.

Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

Abstract: In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line is driven to a high voltage state. The word line is driven to a predetermined voltage state that causes bias temperature instability in the FET. The temperature, the high voltage state on the bit line and the predetermined voltage state on the word line are maintained for an amount of time sufficient to change a threshold voltage of the FET to a state where a desired data value is stored on the FET. The FET is cooled to a second temperature that is cooler than the first temperature after the amount of time has expired.

Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.

Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.