Abstract: A semiconductor device has a FinFET with at least two independently controllable FETs on a single fin. The fin may have a body area with a width between two vertical sides, each side has a single FET. The fin also may have a top fin area that is wider than the body area and is electrically independent from the two FETs. The top fin area may be capable of receiving a body contact structure which may be connected to an electrical conductor as to regulate the voltage in the body area of the fin.

Abstract: A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal.

Abstract: A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.

Abstract: A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes a conductive layer. The conductive layer includes conductive tracks which may be defined by photomasks. The conductive tracks may have quality characteristics. Distinct quality characteristics of distinct conductive tracks may be compared. Based on the comparison, signals and supply voltage may be routed on particular conductive tracks.

Abstract: A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes a conductive layer. The conductive layer includes conductive tracks which may be defined by photomasks. The conductive tracks may have quality characteristics. Distinct quality characteristics of distinct conductive tracks may be compared. Based on the comparison, signals and supply voltage may be routed on particular conductive tracks.

Abstract: A method for fabricating a resistor in a dielectric layer of an integrated circuit (IC) is disclosed. The method may include creating a trench with a first side, a second side opposing the first side, and a bottom, in the dielectric layer, and depositing a conformal film onto the first side, the second side and the bottom of the trench. The method may also include removing the conformal film from the bottom and the second side of the trench, and filling the trench with an insulator. The method may also include removing the conformal film from the first side of the trench to form a receptacle adjacent to the insulator, and depositing electrically resistive material into the receptacle to form a resistor.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.

Abstract: Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node.

Abstract: Methods and structures implement enhanced power supply distribution and decoupling utilizing Through-Silicon-Via (TSV) exclusion zone areas for contacting one or more metal wiring layers on a semiconductor chip. A first wiring level in the TSV exclusion zone area includes a first wiring shape having a first hole of a first diameter. A dielectric includes second hole of a second diameter larger than the first diameter is provided above the first wiring level concentric with the first hole. A via hole extends through the first and second holes and an etch is performed to expose a top surface portion of the first wiring shape. A thin oxide is grown over the entire bore of the hole; an anisotropic etch is provided to remove horizontal portions of the thin oxide, exposing wiring shapes. The via hole is filled with a selected material to make TSV electrical connection to the exposed wiring shape.

Abstract: An apparatus includes a first radiation detector to generate a first signal when a first radiation level is exceeded and a second radiation detector to generate a second signal when a second radiation level is exceeded. The second radiation level is greater than the first radiation level. A first circuit is susceptible to soft errors at the first radiation level and a second circuit is susceptible to soft errors at the second radiation level. A control unit may suspend use of the first circuit and activate use of the second circuit if the first signal is received and the second signal is not received. The first and second circuits may be memory cells or logic circuits.

Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.

Abstract: A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width.

Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.

Abstract: A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area.

Abstract: A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground.

Abstract: A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.

Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

Abstract: A method and structures are provided for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. A deep oxygen implant is provided in a selected region of substrate. A first deep trench and second deep trench are formed above the deep oxygen implant. The first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench. Ion implantation at relatively high ion pressure and annealing is utilized to form highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions.

Abstract: A method and structures are provided for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. A deep oxygen implant is provided in a selected region of substrate. A first deep trench and second deep trench are formed above the deep oxygen implant. The first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench. Ion implantation at relatively high ion pressure and annealing is utilized to form highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions.