Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract: A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Abstract: An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon vias or other interconnects.

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Abstract: A method for correcting of asymmetric shifts in threshold voltage of transistors caused by effects such as negative-bias temperature instability (NBTI) during burn-in. The method may include providing logic patterns to an integrated circuit, such that devices that were stressed during burn-in are relaxed, and devices that suffered less stress during burn-in are stressed.