Patents by Inventor John E. Sheets, II
John E. Sheets, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10592209Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of two received binary numbers. The multiplier circuit includes two sets of inputs that receive binary numbers. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of an AND gate and to a local product output node. Each AND gate is connected to a unique pair of bits, one bit from each of the two binary numbers. Each scaled capacitor has a capacitance proportional to a product term generated by the corresponding AND gate. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.Type: GrantFiled: October 17, 2018Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
-
Patent number: 10587282Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.Type: GrantFiled: May 10, 2019Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
-
Patent number: 10580730Abstract: An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.Type: GrantFiled: November 16, 2017Date of Patent: March 3, 2020Assignee: International Business Machines CorporationInventors: Anthony G. Aipperspach, Jeffrey D. Brown, Kirk D. Peterson, John E. Sheets, II
-
Patent number: 10566987Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.Type: GrantFiled: May 10, 2019Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
-
Publication number: 20200013868Abstract: According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.Type: ApplicationFiled: August 21, 2019Publication date: January 9, 2020Inventors: LAWRENCE A. CLEVENGER, JUNLI WANG, KIRK D. PETERSON, BAOZHEN LI, TERRY A. SPOONER, JOHN E. SHEETS, II
-
Publication number: 20190393886Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.Type: ApplicationFiled: May 10, 2019Publication date: December 26, 2019Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
-
Publication number: 20190393885Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.Type: ApplicationFiled: May 10, 2019Publication date: December 26, 2019Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
-
Publication number: 20190363013Abstract: A semiconductor device includes a first dielectric layer including a first contact hole, a second dielectric layer formed on the first dielectric layer, and including a second contact hole aligned with the first contact hole, and a reflowed copper layer formed in the first and second contact holes.Type: ApplicationFiled: February 28, 2019Publication date: November 28, 2019Inventors: Lawrence A. CLEVENGER, Baozhen LI, Kirk David PETERSON, John E. SHEETS, II, Junli WANG, Chih-Chao YANG
-
Publication number: 20190348361Abstract: An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Anthony G. Aipperspach, Jeffrey D. Brown, Kirk D. Peterson, John E. Sheets, II
-
Patent number: 10468491Abstract: According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.Type: GrantFiled: July 3, 2018Date of Patent: November 5, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Junli Wang, Kirk D. Peterson, Baozhen Li, Terry A. Spooner, John E. Sheets, II
-
Patent number: 10418094Abstract: Predicting data correlation using multivalued logical outputs in SRAM storage cells including generating a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points; writing, into storage cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each storage cell; and measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs.Type: GrantFiled: February 8, 2018Date of Patent: September 17, 2019Assignee: International Business Machines CorporationInventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
-
Patent number: 10367520Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.Type: GrantFiled: June 26, 2018Date of Patent: July 30, 2019Assignee: International Business Machines CorporationInventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
-
Patent number: 10348320Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)* a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.Type: GrantFiled: June 26, 2018Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
-
Patent number: 10304522Abstract: Big data analysis using low power circuit design including storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline; precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit; activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells; and measuring a resulting voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result.Type: GrantFiled: January 31, 2017Date of Patent: May 28, 2019Assignee: International Business Machines CorporationInventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
-
Publication number: 20190148284Abstract: An integrated circuit (IC) can be configured to provide managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within the region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specified, managed voltage, through a VPI, to a set of circuits within a corresponding region of the IC.Type: ApplicationFiled: November 16, 2017Publication date: May 16, 2019Inventors: Anthony G. Aipperspach, Jeffrey D. Brown, Kirk D. Peterson, John E. Sheets, II
-
Patent number: 10256145Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, and forming a copper contact in the first and second contact holes.Type: GrantFiled: December 29, 2017Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
-
Patent number: 10236050Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.Type: GrantFiled: June 6, 2018Date of Patent: March 19, 2019Assignee: International Business Machines CorporationInventors: Karl R. Erickson, Phil C. Paone, George F. Paulik, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
-
Patent number: 10236887Abstract: Generating a unique die identifier for an electronic chip including placing the electronic chip in an identifier generation state, wherein the electronic chip comprises a set of test circuits, wherein each of the set of test circuits is attached to a corresponding component on the electronic chip; obtaining an ordered list of race pairs of the set of test circuits; for each race pair in the ordered list of race pairs of the set of test circuits: selecting the race pair of test circuits; executing a race between the selected race pair; and adding an element to the unique die identifier based on an outcome of the executed race; and returning the electronic chip to an operational state.Type: GrantFiled: November 9, 2017Date of Patent: March 19, 2019Assignee: International Business Machines CorporationInventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
-
Patent number: 10224410Abstract: Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through-substrate via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through-substrate via can also include metal contacts to the collector, base, and emitter which enable the through-substrate via to be coupled to a metal routing layer or a solder bump.Type: GrantFiled: November 7, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, David P. Paulsen, John E. Sheets, II
-
Patent number: 10224089Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.Type: GrantFiled: June 5, 2018Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Karl R. Erickson, Phil C. Paone, George F. Paulik, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann