Patents by Inventor John E. Sheets, II

John E. Sheets, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for testing charge trap memory cells
    Patent number: 9666305
    Abstract: A circuit for testing a memory includes a complementary charge trap memory cell, which includes a first transistor and a second transistor. A logical value of the cell corresponds to respective states of the first transistor and the second transistor. The circuit further includes a first bitline coupled to the first transistor, where the first transistor is configured to apply a first voltage to the first bitline. The circuit includes a second bitline coupled to the second transistor, where the second transistor is configured to apply a second voltage to the second bitline. The circuit also includes a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first voltage on the first bitline and the second voltage on the second bitline.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • IMPLEMENTING EFUSE VISUAL SECURITY OF STORED DATA USING EDRAM
    Publication number: 20170148527
    Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuitry having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.
    Type: Application
    Filed: March 8, 2016
    Publication date: May 25, 2017
    Inventors: Todd A. Christensen, Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Implementing eFuse visual security of stored data using EDRAM
    Patent number: 9646712
    Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuitry having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Todd A. Christensen, Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • METHOD OF OPTIMIZING WIRE RC FOR DEVICE PERFORMANCE AND RELIABILITY
    Publication number: 20170098577
    Abstract: A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.
    Type: Application
    Filed: October 1, 2015
    Publication date: April 6, 2017
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Terry A. Spooner
  • Multiple FET non-volatile memory with default logical state
    Patent number: 9589639
    Abstract: A memory array has a NVM element with a plurality of FETs. A first set of FETs of the plurality of FETs is coupled to a bitline true of the memory array. The first set of FETs has a first channel width. A second set of FETs of the plurality of FETs is coupled to a bitline complement of the memory array. The second set of FETs has a second channel width. The first channel width is greater than the second channel width. The channel width disparity provides the NVM element of the unprogrammed memory array with a default state.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Robert E. Kilker, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage
    Patent number: 9583403
    Abstract: A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Implementing hidden security key in eFuses
    Patent number: 9570193
    Abstract: A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. The circuit includes a race condition circuit coupled to a latching structure. The race condition circuit is characterized including respective driver strengths of each stage in the race as well as a sampling clock during chip testing. The data is used to store drive strengths for each stage in eFuses and is used to get a logical one or logical zero out of the final latching stage of the race condition circuit.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • FinFET power supply decoupling
    Patent number: 9570388
    Abstract: Embodiments herein describe dummy gates disposed over a portion of a fin in finFETs. That is, instead of separating the dummy gates from the finFET structure, the fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor. In one embodiment, the dummy gate overlaps a portion of the fin that is held at a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than rail coupled to the fin. For example, if the fin is coupled to VHIGH then the dummy gate is coupled to VLOW, or vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., VHIGH and VLOW).
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Todd A. Christensen, John E. Sheets, II
  • FINFET POWER SUPPLY DECOUPLING
    Publication number: 20160379928
    Abstract: Embodiments herein describe dummy gates disposed over a portion of a fin in finFETs. That is, instead of separating the dummy gates from the finFET structure, the fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor. In one embodiment, the dummy gate overlaps a portion of the fin that is held at a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than rail coupled to the fin. For example, if the fin is coupled to VHIGH then the dummy gate is coupled to VLOW, or vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., VHIGH and VLOW).
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Todd A. CHRISTENSEN, John E. SHEETS, II
  • IMPLEMENTING RESISTANCE DEFECT PERFORMANCE MITIGATION USING TEST SIGNATURE DIRECTED SELF HEATING AND INCREASED VOLTAGE
    Publication number: 20160379898
    Abstract: A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • IMPLEMENTING RESISTANCE DEFECT PERFORMANCE MITIGATION USING TEST SIGNATURE DIRECTED SELF HEATING AND INCREASED VOLTAGE
    Publication number: 20160379899
    Abstract: A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 29, 2016
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Power gating and clock gating in wiring levels
    Patent number: 9520876
    Abstract: A semiconductor comprising a front end of line portion including a logical processing unit (LPU) and a second LPU. The first LPU configured to perform a first operation and the second LPU configured to perform a second operation following the first operation. A back end of line portion including a plurality of wiring levels, and further including a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels. The power gate and clock gate are further electrically connected to the first LPU by an enable wire. The power gate and clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU. A signal wire is electrically connected to the first LPU and to the latch.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel R. Chadwick, Tassbieh Hassan, Kirk D. Peterson, John E. Sheets, II, Christine E. Whiteside
  • Implementing eFuse visual security of stored data using EDRAM
    Patent number: 9514841
    Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuity having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Todd A. Christensen, Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • High-density integrated circuit via capacitor
    Patent number: 9496326
    Abstract: A capacitor can be fabricated within an integrated circuit (IC) by creating, in a top surface of a dielectric layer of the IC, a recess having at least one side and a bottom, the bottom adjacent to a first conductive structure. A first plate of the capacitor may be formed by depositing a conductive liner onto the at least one side and the bottom of the recess. A conformal dielectric film may be deposited onto the first plate within the recess, and a second plate of the capacitor may be formed by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the first plate.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Todd A. Christensen, John E. Sheets, II
  • Sensing of non-volatile memory cell having two complementary memory transistors
    Patent number: 9496045
    Abstract: Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Kilker, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • High-density integrated circuit via capacitor
    Patent number: 9455313
    Abstract: A capacitor can be fabricated within an integrated circuit (IC) by creating, in a top surface of a dielectric layer of the IC, a recess having at least one side and a bottom, the bottom adjacent to a first conductive structure. A first plate of the capacitor may be formed by depositing a conductive liner onto the at least one side and the bottom of the recess. A conformal dielectric film may be deposited onto the first plate within the recess, and a second plate of the capacitor may be formed by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the first plate.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Todd A. Christensen, John E. Sheets, II
  • Decoupling capacitor using finFET topology
    Patent number: 9455251
    Abstract: Embodiments herein describe a decoupling capacitor that may include multiple fin and gate structures electrically insulated from a conductor (e.g., a metal layer) by a thin dielectric. The fins and gates may be electrically coupled to a first voltage rail (e.g., VHIGH) while the conductor is coupled to a second voltage rail (e.g., VLOW). In this manner, the fins and gates in combination form a first “plate” which is electrically insulated from the conductor which forms a second “plate” of a capacitor. In one embodiment, the decoupling capacitor is formed on the same substrate as the finFETs, and thus, can be disposed proximate to the finFETs—e.g., on the same layer in the chip or side-by-side. In one example, at least a portion of the decoupling capacitor and the finFET may be formed using the same fabrication steps.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Todd A. Christensen, John E. Sheets, II
  • Structure for metal oxide semiconductor capacitor
    Patent number: 9443767
    Abstract: A design structure for a semiconductor structure is disclosed. The semiconductor structure can include a substrate, a set of semiconductor fins positioned on the substrate and positioned approximately parallel lengthwise to one another, a first gate layer and a second gate layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The semiconductor structure can include an interconnect layer deposited on the substrate and on the set of semiconductor fins approximately perpendicular lengthwise to the set of semiconductor fins. The interconnect layer can be positioned between the first gate layer and the second gate layer at a first interconnect distance from the first gate layer and a second interconnect distance from the second gate layer.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Detection of initial state by eFuse array
    Patent number: 9424948
    Abstract: An array of eFuses without a default state of logical one or logical zero includes rows and columns. One of the rows has data cells for programming as well as indicator data cells for indicating if the programmable data cells have been programmed. Each column includes a sense amplifier to sense the state of cells of the column. Sense amplifiers of columns with indicator data cells are coupled to one or more logic gates which determine if the indicator data cells are in a selected logical state. Sense amplifiers of columns with data cells are coupled to mask logic gates. The mask logic gates are coupled to both columns of data cells and outputs of the one or more logic gates. The logic gates mask outputs of the data cells when the indicator data cells are not in the selected logical state.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Bias-temperature induced damage mitigation circuit
    Patent number: 9405311
    Abstract: A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: David M. Onsongo, David P. Paulsen, Kirk D. Peterson, John E. Sheets, II