Abstract: Techniques are provided for sensing a signal associated with a memory cell capable of storing three or more logic states. To sense a state of the memory cell, a charge may be transferred between a digit line and a node coupled with a plurality of sense components using a charge transfer device. Once the charge is transferred, one or more of the plurality of sense components may sense the charge with one of a variety of sensing schemes. Based on the charge being transferred using the charge transfer device and each sense component sensing the charge, a logic state associated with the memory cell may be determined. The number of sensed states may be correlated to the number of sense amplifiers. The ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than one.

Abstract: Systems, devices, and methods for charging a node of a sense component during an access operation are described. The node of the sense component may be coupled with a charge transfer device and with a voltage source using a switching component. The voltage source may be configured to output different voltages (e.g., two different precharge voltages) during different phases of the access operation. The switching component may be configured to selectively couple the node with the voltage source and the different voltages may be used to precharge the node during different phases of the access operation. The different voltages of the voltage source may provide an adequate sense window.

Abstract: Techniques are provided for writing a high-level state to a memory cell capable of storing three or more logic states. After a sense operation performed by a first sense component and a second sense component, a digit line may be isolated from the first sense component and the second sense component. The high-level state may be stored in the memory cell, then a second state may be stored in the memory cell, in which the second state may be a mid-level state or a low-level state. The second state may be stored based on a write-back component identifying that the second state was stored in the memory cell before the write back procedure.

Abstract: Techniques are provided for sensing a signal associated with a memory cell capable of storing three or more logic states. To sense a state of the memory cell, a charge may be transferred between a digit line and a node coupled with a plurality of sense components using a charge transfer device. Once the charge is transferred, one or more of the plurality of sense components may sense the charge with one of a variety of sensing schemes. Based on the charge being transferred using the charge transfer device and each sense component sensing the charge, a logic state associated with the memory cell may be determined. The number of sensed states may be correlated to the number of sense amplifiers. The ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than one.

Abstract: Techniques are provided for sensing a signal associated with a memory cell capable of storing three or more logic states. To sense the memory cell (e.g., a signal associated with the memory cell), a charge may be transferred between a digit line and a node coupled with a plurality of sense components using a charge transfer device. Once the charge is transferred, at least some if not each of the plurality of sense components may sense the charge using one of a variety of sensing schemes. For example, the charge may be sensed by each sense component at a same time using a single fixed reference value, or at different times using different fixed reference values. Based on the charge being transferred or transferred with the node (e.g., using the charge transfer device) and each sense component sensing the charge, a logic state associated with the memory cell may be determined.

Abstract: Systems, devices, and methods for charging a node of a sense component during an access operation are described. The node of the sense component may be coupled with a charge transfer device and with a voltage source using a switching component. The voltage source may be configured to output different voltages (e.g., two different precharge voltages) during different phases of the access operation. The switching component may be configured to selectively couple the node with the voltage source and the different voltages may be used to precharge the node during different phases of the access operation. The different voltages of the voltage source may provide an adequate sense window.

Abstract: Techniques are provided for sensing a signal associated with a memory cell capable of storing one of three or more logic states. To sense the memory cell (e.g., to sense the signal associated with the memory cell), a first sense component may compare the signal with a first reference value. A reference selector may select a second reference value based on the comparison of the signal with the first reference value. A second sense component may compare the signal with the second reference value. The logic state of the memory cell may be determined based on the results of the first comparison and the second comparison.

Abstract: Devices and methods for a sensing scheme are described. A device may include a memory array and a column select line configured to couple with a single page of a set of pages within the memory array when the single page is selected during an access operation. The column select line may be isolated from other pages (e.g., unselected pages) of the set. The device may include a set of sense component groups coupled with the single page. Each sense component group of the set may be configured to access one or more memory cells of the single page using the column select line. The device may include a decoding component configured to couple a sense component group of the set with an I/O line of an I/O channel. The device may communicate information with the I/O line during the access operation.

Abstract: Techniques are provided for reading a memory cell capable of storing three or more logic states. To read the memory cell, a charge may be transferred between a digit line and a sense component using a charge transfer device. The charge may be transferred by biasing a gate of the charge transfer device to a first voltage and discharging the memory cell onto the digit line, which may result in the digit line being biased to a second voltage. Based on whether the second voltage exceeds the first voltage, the charge transfer device may transfer the charge associated with the memory cell (e.g., and discharged onto the digit line) to the sense component. A charge may be transferred from a memory cell to a sense component based on a value of the logic state stored to the memory cell.

Abstract: Techniques are provided for sensing a signal associated with a memory cell capable of storing one of three or more logic states. To sense the memory cell (e.g., to sense the signal associated with the memory cell), a first sense component may compare the signal with a first reference value. A reference selector may select a second reference value based on the comparison of the signal with the first reference value. A second sense component may compare the signal with the second reference value. The logic state of the memory cell may be determined based on the results of the first comparison and the second comparison.

Abstract: Devices and methods for sensing a memory cell using a charge transfer device are described. In some examples, the charge transfer device may be coupled with an input transistor of a differential transistor pair that may be coupled with a sense component. The differential transistor pair may be configured to isolate the sense component from the charge transfer device during a read operation. To read the memory cell, a gate of the charge transfer device may be charged to a first voltage. Subsequently, a digit line may be biased to a second voltage by discharging the memory cell onto the digit line. A charge may be transferred, using the charge transfer device, between the digit line and a gate of the input transistor such that the sense component may determine a logic state stored on the memory cell based on the first voltage and the second voltage.

Abstract: Techniques are provided for tuning the voltages of a circuit for reading a memory cell capable of storing three or more logic states. To read the memory cell, a charge may be transferred between a digit line and a sense component using a charge transfer device. The gate of the charge transfer device may initially be biased to a first voltage and subsequently tuned to a second voltage to optimize the sense window. After biasing the gate of the charge transfer device to the second voltage, the memory cell may discharge its charge onto the digit line, which may result in the digit line being biased to a third voltage. Based on whether the third voltage exceeds the second voltage, the charge transfer device may transfer the charge associated with the memory cell.

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Abstract: Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word.

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Abstract: Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract: Some embodiments include apparatuses and methods having an input node to receive a first voltage, an output node to provide an output voltage, and a charge pump to generate the output voltage based on the first voltage. The charge pump can include a control node to receive a control signal for controlling at least one switch of the charge pump, such that the output voltage includes a value greater than a value of the first voltage. The control signal can include a level corresponding to a second voltage having a value greater than the value of the output voltage. Additional apparatus and methods are described.